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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Daniel Machon <[email protected]>
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
23 * Adjustable tx de-emphasis (FFE)
32 The SERDES6G is a high-speed SERDES interface, which can operate at
35 * 100 Mbps (100BASE-FX)
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <[email protected]>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
/linux-6.14.4/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
37 #define MDIO_DEVS1 5 /* Devices in package */
50 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <[email protected]>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <[email protected]>
11 - Russell King <[email protected]>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
[all …]
/linux-6.14.4/Documentation/networking/
Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
208 Now just make sure that phydev->supported and phydev->advertising have any
[all …]
/linux-6.14.4/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/linux-6.14.4/drivers/phy/mediatek/
Dphy-mtk-xfi-tphy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MediaTek 10GE SerDes XFI T-PHY driver
6 * Bc-bocun Chen <bc-[email protected]>
7 * based on mtk_usxgmii.c and mtk_sgmii.c found in MediaTek's SDK (GPL-2.0)
22 #include "phy-mtk-io.h"
27 #define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x)) argument
29 #define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x)) argument
33 #define XTP_PCS_PWD_SYNC(x) FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x)) argument
35 #define XTP_PCS_PWD_ASYNC(x) FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x)) argument
44 #define XFI_DPHY_AD_SGDT_FRC_EN BIT(5)
[all …]
/linux-6.14.4/drivers/net/dsa/mv88e6xxx/
Dserdes.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 /* 10GBASE-R and 10GBASE-X4/X2 */
61 /* 1000BASE-X and SGMII */
107 #define MV88E6393X_SERDES_POC_PDOWN BIT(5)
146 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
150 if (!chip->info->ops->serdes_get_lane) in mv88e6xxx_serdes_get_lane()
151 return -EOPNOTSUPP; in mv88e6xxx_serdes_get_lane()
153 return chip->info->ops->serdes_get_lane(chip, port); in mv88e6xxx_serdes_get_lane()
159 if (!chip->info->ops->serdes_irq_mapping) in mv88e6xxx_serdes_irq_mapping()
162 return chip->info->ops->serdes_irq_mapping(chip, port); in mv88e6xxx_serdes_irq_mapping()
Dserdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 state->link = false; in mv88e6xxx_pcs_decode_state()
53 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_pcs_decode_state()
54 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); in mv88e6xxx_pcs_decode_state()
61 state->duplex = status & in mv88e6xxx_pcs_decode_state()
66 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_pcs_decode_state()
68 state->pause |= MLO_PAUSE_RX; in mv88e6xxx_pcs_decode_state()
72 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) in mv88e6xxx_pcs_decode_state()
73 state->speed = SPEED_2500; in mv88e6xxx_pcs_decode_state()
75 state->speed = SPEED_1000; in mv88e6xxx_pcs_decode_state()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/marvell/
Dcn9132-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9132-sr-cex7.dtsi"
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
32 gpio-keys {
33 compatible = "gpio-keys";
[all …]
Darmada-7040-mochabin.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-7040.dtsi"
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
34 sfp_eth0: sfp-eth0 {
36 i2c-bus = <&cp0_i2c1>;
37 los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
[all …]
Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/linux-6.14.4/drivers/phy/microchip/
Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
21 gbase, ginst, gcnt, gwidth, \ argument
23 (gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth))
80 SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA,
113 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
118 HSIO_HW_CFG_GMII_ENA_SET(BIT(5))),
189 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | in lan966x_sd6g40_reg_cfg()
190 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | in lan966x_sd6g40_reg_cfg()
191 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | in lan966x_sd6g40_reg_cfg()
[all …]
/linux-6.14.4/drivers/net/phy/
Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
178 return phydev->drv->driver_data; in to_mv3310_chip()
[all …]
Dbcm84881.c1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
34 unsigned long *possible = phydev->possible_interfaces; in bcm84881_fill_possible_interfaces()
45 switch (phydev->interface) { in bcm84881_config_init()
51 return -ENODEV; in bcm84881_config_init()
62 if (!phydev->is_c45 || in bcm84881_probe()
63 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in bcm84881_probe()
[all …]
Dair_en8811h.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - Only full duplex supported
7 * - Forced speed (AN off) is not supported by hardware (100Mbps)
85 #define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
97 #define AIR_PHY_LED_BLINK_10RX BIT(5)
116 #define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
128 * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx
129 * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps
130 * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps
246 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_write()
[all …]
Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
44 * struct phylink - internal data type for phylink
61 u8 link_port; /* The current non-phy ethtool port */
103 if ((pl)->config->type == PHYLINK_NETDEV) \
104 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
105 else if ((pl)->config->type == PHYLINK_DEV) \
106 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
118 if ((pl)->config->type == PHYLINK_NETDEV) \
119 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
[all …]
/linux-6.14.4/include/linux/
Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
64 * Set phydev->irq to PHY_POLL if interrupts are not supported,
68 #define PHY_POLL -1
69 #define PHY_MAC_INTERRUPT -2
78 * enum phy_interface_t - Interface Mode definitions
80 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
82 * @PHY_INTERFACE_MODE_MII: Media-independent interface
83 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
84 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
[all …]
/linux-6.14.4/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
32 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5)
42 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
69 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
71 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5)
82 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
108 /* Relative to priv->regmap */
[all …]
/linux-6.14.4/drivers/net/
Dmdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mdio.c: Generic support for MDIO-compatible transceivers
4 * Copyright 2006-2009 Solarflare Communications Inc.
14 MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers");
15 MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc.");
19 * mdio45_probe - probe for an MDIO (clause 45) device
32 for (mmd = 1; mmd <= 5; mmd++) { in mdio45_probe()
34 stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2); in mdio45_probe()
40 devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1); in mdio45_probe()
41 devs2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS2); in mdio45_probe()
[all …]
/linux-6.14.4/drivers/net/ethernet/amd/xgbe/
Dxgbe-phy-v2.c125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
225 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
320 XGBE_PHY_REDRV_MODE_CX = 5,
375 /* Re-driver support */
[all …]
/linux-6.14.4/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_83xx_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
38 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
39 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
40 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
50 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
51 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
52 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
53 #define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
77 {QLCNIC_CMD_WRITE_PHY, 5, 1},
[all …]
/linux-6.14.4/drivers/net/usb/
Daqc111.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Aquantia Corp. Aquantia AQtion USB to 5GbE Controller
3 * Copyright (C) 2003-2005 David Hollis <[email protected]>
5 * Copyright (C) 2002-2003 TiVo Inc.
6 * Copyright (C) 2017-2018 ASIX
34 netdev_warn(dev->net, in aqc111_read_cmd_nopm()
35 "Failed to read(0x%x) reg index 0x%04x: %d\n", in aqc111_read_cmd_nopm()
50 netdev_warn(dev->net, in aqc111_read_cmd()
51 "Failed to read(0x%x) reg index 0x%04x: %d\n", in aqc111_read_cmd()
82 int err = -ENOMEM; in __aqc111_write_cmd()
[all …]
Dcdc_ether.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2003-2005 by David Brownell
26 return (desc->bInterfaceClass == USB_CLASS_COMM && in is_rndis()
27 desc->bInterfaceSubClass == 2 && in is_rndis()
28 desc->bInterfaceProtocol == 0xff); in is_rndis()
33 return (desc->bInterfaceClass == USB_CLASS_MISC && in is_activesync()
34 desc->bInterfaceSubClass == 1 && in is_activesync()
35 desc->bInterfaceProtocol == 1); in is_activesync()
40 return (desc->bInterfaceClass == USB_CLASS_WIRELESS_CONTROLLER && in is_wireless_rndis()
41 desc->bInterfaceSubClass == 1 && in is_wireless_rndis()
[all …]

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