Home
last modified time | relevance | path

Searched +full:3 +full:gbps (Results 1 – 25 of 174) sorted by relevance

1234567

/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
19 Two set of 3-tuple setting for each (up to 3)
25 Two set of 3-tuple setting for each (up to 3)
27 - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
28 gain control. Two set of 3-tuple setting for each
29 (up to 3) supported link speed on the host. Range is
30 between 0 to 31 in unit of dB. Default is 3.
31 - apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
[all …]
/linux-6.14.4/drivers/scsi/mvsas/
Dmv_94xx.h72 /* ports 1-3 follow after this */
79 /* ports 1-3 follow after this */
84 /* ports 1-3 follow after this */
91 /* phys 1-3 follow after this */
94 /* phys 1-3 follow after this */
123 VSR_PHY_MODE11 = 0x0B * 4, /* Event Counter 3 */
144 MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96712.yaml21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
55 port@3:
57 description: GMSL Input 3
115 data-lanes = <1 2 3 4>;
Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
123 data-lanes = <1 2 3 4>;
149 data-lanes = <1 2 3 4>;
Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
132 data-lanes = <1 2 3 4>;
Dovti,ov08x40.yaml19 - 4-lane MIPI D-PHY TX @ 1 Gbps per lane
20 - 2-lane MPIP D-PHY TX @ 2 Gbps per lane
67 - const: 3
114 data-lanes = <1 2 3 4>;
Dsony,imx214.yaml16 maximum throughput of 1.2Gbps/lane.
72 - const: 3
117 data-lanes = <1 2 3 4>;
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_arcturus.h59 #define FEATURE_DPM_SOCCLK_BIT 3
190 #define THROTTLER_TEMP_MEM_BIT 3
215 #define WORKLOAD_PPLIB_COMPUTE_BIT 3
312 uint8_t Padding[3];
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
Dsmu11_driver_if_sienna_cichlid.h79 #define FEATURE_DPM_UCLK_BIT 3
198 #define THROTTLER_TEMP_MEM_BIT 3
222 #define FW_DSTATE_MP0_DS_BIT 3
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
530 XGMI_LINK_RATE_18 = 18, // 18Gbps
[all …]
/linux-6.14.4/drivers/net/ethernet/ezchip/
Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
67 #define CFG_0_TX_PAD_EN_SHIFT 3
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
127 #define CFG_3_REDIRECT_CBFC_SEL_SHIFT 3
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml21 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
22 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
29 The SparX-5 switch family targets managed Layer 2 and Layer 3
135 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
136 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
144 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
145 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
/linux-6.14.4/tools/testing/selftests/drivers/net/mlxsw/
Dsch_red_core.sh3 # This test sends a >1Gbps stream of traffic from H1, to the switch, which
4 # forwards it to a 1Gbps port. This 1Gbps stream is then looped back to the
5 # switch and forwarded to the port under test $swp3, which is also 1Gbps.
35 # | >1Gbps |
60 # | | | 1Gbps
142 # 1Gbps.
151 host_create $h3 3
264 ping_test $h1.10 $(ipaddr 3 10) " from host 1, vlan 10"
265 ping_test $h1.11 $(ipaddr 3 11) " from host 1, vlan 11"
266 ping_test $h2.10 $(ipaddr 3 10) " from host 2, vlan 10"
[all …]
Dqos_mc_aware.sh39 # | >1Gbps | | >1Gbps |
48 # | | 1Gbps bottleneck |
133 tc qdisc replace dev $swp3 root handle 3: tbf rate 1gbit \
135 defer tc qdisc del dev $swp3 root handle 3:
137 tc qdisc replace dev $swp3 parent 3:3 handle 33: \
139 defer tc qdisc del dev $swp3 parent 3:3 handle 33:
260 # degradation on 1Gbps link.
Dqos_ets_strict.sh24 # | >1Gbps | | >1Gbps |
33 # | | 1Gbps bottleneck |
114 lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:1,2:2,3:3,4:4,5:5,6:6,7:7
115 defer lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:0,2:0,3:0,4:0,5:0,6:0,7:0
121 )"3:strict,"$(
/linux-6.14.4/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.c291 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
295 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
299 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
310 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
314 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
318 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
325 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
330 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
335 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
405 /* Reset PHY 3 times in a row */ in dw_hdmi_phy_init()
/linux-6.14.4/include/rdma/
Dopa_port_info.h30 #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3
87 /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
110 #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3)
119 OPA_PORT_PHYS_CONF_VARIABLE = 3,
217 OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3),
229 OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3),
259 u8 cap; /* 3 res, 5 bits */
[all …]
/linux-6.14.4/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.h139 #define HCLGE_VF_ID_S 3
140 #define HCLGE_VF_ID_M GENMASK(10, 3)
143 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
190 #define HCLGE_SUPPORT_50G_R2_BIT BIT(3)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/marvell/
Darmada-8040-puzzle-m801.dts37 v_3_3: regulator-3-3v {
80 los-gpios = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>;
108 /* SFP+ port 2: 10 Gbps indicator */
114 led-3 {
115 /* SFP+ port 2: 1 Gbps indicator */
117 function-enumerator = <3>;
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_cx0_phy.c253 /* 3 tries is assumed to be enough to read successfully */ in __intel_cx0_read()
254 for (i = 0; i < 3; i++) { in __intel_cx0_read()
344 /* 3 tries is assumed to be enough to write successfully */ in __intel_cx0_write()
345 for (i = 0; i < 3; i++) { in __intel_cx0_write()
472 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
531 .pll[3] = 0x1,
557 .pll[3] = 0x1,
583 .pll[3] = 0x1,
609 .pll[3] = 0x0,
635 .pll[3] = 0x1,
[all …]
/linux-6.14.4/drivers/net/phy/realtek/
Drealtek_main.c40 #define RTL8211F_LEDCR_LINK_1000 BIT(3)
47 #define RTL8211F_RX_DELAY BIT(3)
92 #define RTL_VND2_PHYSR_DUPLEX BIT(3)
105 #define RTL8211F_LED_COUNT 3
671 /* bit 3 in rtlgen_decode_physr()
1431 .name = "RTL8226 2.5Gbps PHY",
1442 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1454 .name = "RTL8226-CG 2.5Gbps PHY",
1464 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1476 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
[all …]
/linux-6.14.4/fs/smb/client/
Dcifs_debug.c180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
196 return "50Gbps"; in smb_speed_to_str()
198 return "56Gbps"; in smb_speed_to_str()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_capability.c143 case 0x20: // 3 lttpr repeaters in dp_parse_lttpr_repeater_count()
144 return 3; in dp_parse_lttpr_repeater_count()
184 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. in linkRateInKHzToLinkRateMultiplier()
187 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
190 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
193 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
196 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
199 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
202 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
205 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
[all …]
/linux-6.14.4/Documentation/networking/device_drivers/ethernet/pensando/
Dionic.rst36 ionic 0000:b5:00.0 enp181s0: Link up - 100 Gbps
39 ionic 0000:b6:00.0 enp182s0: Link up - 100 Gbps
145 rx_csum_complete: 3
156 tx_0_pkts: 3
158 tx_0_clean: 3
166 tx_0_csum_none: 3
212 frames_rx_vlan_good: 3
/linux-6.14.4/drivers/usb/host/
Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
87 ssac = 3; in xhci_create_usb3x_bos_desc()
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
[all …]

1234567