Searched +full:25 +full:gbase +full:- +full:sr (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Steen Hegelund <[email protected]>11 - Daniel Machon <[email protected]>22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)23 * Adjustable tx de-emphasis (FFE)32 The SERDES6G is a high-speed SERDES interface, which can operate at35 * 100 Mbps (100BASE-FX)[all …]
1 // SPDX-License-Identifier: GPL-2.0-only14 * struct sfp_bus - internal representation of a sfp bus36 * sfp_parse_port() - Parse the EEPROM base ID, setting the port type43 * %PORT_TP, %PORT_FIBRE or %PORT_OTHER. If @support is non-%NULL,55 switch (id->base.connector) { in sfp_parse_port()76 if (id->base.e1000_base_t) { in sfp_parse_port()88 dev_warn(bus->sfp_dev, "SFP: unknown connector id 0x%02x\n", in sfp_parse_port()89 id->base.connector); in sfp_parse_port()111 * sfp_may_have_phy() - indicate whether the module may have a PHY120 if (id->base.e1000_base_t) in sfp_may_have_phy()[all …]
3 * Copyright (c) 2007-2013 Broadcom Corporation13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be20 * WR - Write Clear (write 1 to clear the bit)32 /* [RW 1] Initiate the ATC array - reset all the valid bits */56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -[all …]