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/linux-6.14.4/arch/m68k/include/uapi/asm/
Dbootinfo-hp300.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-hp300.h -- HP9000/300-specific boot information definitions
11 * HP9000/300-specific tags
25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
[all …]
/linux-6.14.4/arch/arm/mach-omap2/
Dopp2xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-[email protected]>
34 * struct prcm_config - define clock rates on a per-OPP basis (24xx)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
64 /*-------------------------------------------------------------------------
66 *-------------------------------------------------------------------------*/
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
[all …]
Dtimer.c2 * linux/arch/arm/mach-omap2/timer.c
16 * OMAP Dual-mode timer framework support by Timo Teras
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
23 * Added OMAP4 support - Santosh Shilimkar <[email protected]>
35 #include "omap-secure.h"
50 * The realtime counter also called master counter, is a free-running
53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
121 den = 25; in realtime_counter_init()
[all …]
/linux-6.14.4/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
52 mode "640x480-75"
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <[email protected]>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
[all …]
Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
[all …]
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <[email protected]>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
[all …]
Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <[email protected]>
11 - Florian Fainelli <[email protected]>
12 - Heiner Kallweit <[email protected]>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
[all …]
/linux-6.14.4/drivers/clk/uniphier/
Dclk-uniphier-sys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
[all …]
/linux-6.14.4/arch/arm/boot/dts/arm/
Dintegratorcp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
49 /* The codec chrystal operates at 24.576 MHz */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dsophgo,sg2042-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen Wang <[email protected]>
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
25 clock-names:
[all …]
Dstarfive,jh7100-clkgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <[email protected]>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
[all …]
/linux-6.14.4/drivers/clk/spear/
Dspear1340_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1340_clock.c
107 #define SPEAR1340_DMA_CLK_ENB 25
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
[all …]
Dspear1310_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-spear13xx/spear1310_clock.c
109 #define SPEAR1310_DMA_CLK_ENB 25
200 #define SPEAR1310_CAN1_CLK_ENB 25
231 /* PCLK 24MHz */
232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
[all …]
/linux-6.14.4/drivers/media/tuners/
Dqt1010.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 { .addr = priv->cfg->i2c_address, in qt1010_readreg()
17 { .addr = priv->cfg->i2c_address, in qt1010_readreg()
21 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in qt1010_readreg()
22 dev_warn(&priv->i2c->dev, "%s: i2c rd failed reg=%02x\n", in qt1010_readreg()
24 return -EREMOTEIO; in qt1010_readreg()
33 struct i2c_msg msg = { .addr = priv->cfg->i2c_address, in qt1010_writereg()
36 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in qt1010_writereg()
37 dev_warn(&priv->i2c->dev, "%s: i2c wr failed reg=%02x\n", in qt1010_writereg()
39 return -EREMOTEIO; in qt1010_writereg()
[all …]
Dqt1010_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux-6.14.4/drivers/clk/qcom/
Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
17 * with 31.25 MHZ.
19 * +---------+
21 * +--+---+--+
24 * +-------+---+------+
[all …]
/linux-6.14.4/drivers/clk/mvebu/
Darmada-375.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
144 CLK_OF_DECLARE(armada_375_core_clk, "marvell,armada-375-core-clock",
[all …]
Darmada-39x.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include <linux/clk-provider.h>
24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
115 return 25 * 1000 * 1000; in armada_39x_refclk_ratio()
131 CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
[all …]
/linux-6.14.4/drivers/clk/versatile/
Dclk-icst.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
37 * struct clk_icst - ICST VCO clock wrapper
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
77 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and in vco_get()
78 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. in vco_get()
80 if (icst->ctype == ICST_INTEGRATOR_AP_CM) { in vco_get()
[all …]
/linux-6.14.4/drivers/net/ethernet/intel/ice/
Dice_ptp_consts.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2018-2021, Intel Corporation. */
94 .serdes = 0xffffc59a, /* -29.2 */
95 .no_fec = 0xffff0a80, /* -122.75 */
113 .serdes = 0xffffe8a4, /* -11.68 */
114 .no_fec = 0xffff9a76, /* -50.77 */
132 .serdes = 0xffffeb27, /* -10.42424 */
133 .no_fec = 0xffffcccd, /* -25.6 */
134 .fc = 0xfffc557b, /* -469.26 */
163 .mktime = 0x147b, /* 10.24, only if RS-FEC enabled */
[all …]
/linux-6.14.4/drivers/clk/sophgo/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
9 The driver require a 25MHz Oscillator to function generate clock.
19 frequency of 25 MHz as input, which are used for Main/Fixed
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
40 * ------------------------------------------------
41 *| MII | n/a | 25Mhz |
43 * ------------------------------------------------
44 *| GMII | 125Mhz | 25Mhz |
45 *| | clk-125/txclk | txclk |
46 * ------------------------------------------------
47 *| RGMII | 125Mhz | 25Mhz |
[all …]
/linux-6.14.4/drivers/net/dsa/sja1105/
Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <[email protected]>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/mvm/tests/
Dlinks.c1 // SPDX-License-Identifier: GPL-2.0-only
80 .signal = -100,
89 .signal = -84,
98 .signal = -50,
107 .signal = -66,
117 .signal = -61,
128 .signal = -66,
133 { .desc = "HB, 80 MHz, no channel load factor, punctured percentage 0",
139 .signal = -72,
142 { .desc = "HB, 160 MHz, no channel load factor, punctured percentage 25",
[all …]

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