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/linux-6.14.4/arch/arc/include/asm/
Duaccess.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -__clear_user( ) called multiple times during elf load was byte loop
10 * -Hand crafted constant propagation for "constant" copy sizes
11 * -stock kernel shrunk by 33K at -O3
14 * -Added option to (UN)inline copy_(to|from)_user to reduce code sz
15 * -kernel shrunk by 200K even at -O3 (gcc 4.2.1)
16 * -Enabled when doing -Os
33 case 2: __arc_get_user_one(*(k), u, "ldw", __ret); break; \
34 case 4: __arc_get_user_one(*(k), u, "ld", __ret); break; \
[all …]
/linux-6.14.4/arch/arm64/crypto/
Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
17 .set .Lv\b\().2d, \b
37 * The SHA-512 round constants
40 .align 4
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
91 add v\i3\().2d, v\i3\().2d, v5.2d
[all …]
Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <[email protected]>
7 * it under the terms of the GNU General Public License version 2 as
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
17 * the Free Software Foundation; either version 2 of the License, or
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
42 ld1 {v12.4s}, [x10]
46 add v0.4s, v0.4s, v1.4s
51 add v2.4s, v2.4s, v3.4s
[all …]
/linux-6.14.4/lib/
Dutil_macros_kunit.c1 // SPDX-License-Identifier: GPL-2.0+
23 static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 }; in test_find_closest()
25 1, 2, 4, 8, 16, 32, 64, 128, in test_find_closest()
27 static u32 wd_timeout_table[] = { 2, 4, 6, 8, 16, 32, 48, 64 }; in test_find_closest()
28 static int array_prog1a[] = { 1, 2, 3, 4, 5 }; in test_find_closest()
29 static u32 array_prog1b[] = { 2, 3, 4, 5, 6 }; in test_find_closest()
30 static int array_prog1mix[] = { -2, -1, 0, 1, 2 }; in test_find_closest()
32 static u32 array_prog2b[] = { 2, 4, 6, 8 }; in test_find_closest()
33 static int array_prog3a[] = { 1, 4, 7, 10 }; in test_find_closest()
34 static u32 array_prog3b[] = { 2, 5, 8, 11 }; in test_find_closest()
[all …]
/linux-6.14.4/tools/arch/arm64/include/asm/
Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
21 * C5.2, version:ARM DDI 0487A.f)
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
[all …]
/linux-6.14.4/drivers/media/test-drivers/vicodec/
Dcodec-v4l2-fwht.c1 // SPDX-License-Identifier: LGPL-2.1
11 #include "codec-v4l2-fwht.h"
14 { V4L2_PIX_FMT_YUV420, 1, 3, 2, 1, 1, 2, 2, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
15 { V4L2_PIX_FMT_YVU420, 1, 3, 2, 1, 1, 2, 2, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
16 { V4L2_PIX_FMT_YUV422P, 1, 2, 1, 1, 1, 2, 1, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
17 { V4L2_PIX_FMT_NV12, 1, 3, 2, 1, 2, 2, 2, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
18 { V4L2_PIX_FMT_NV21, 1, 3, 2, 1, 2, 2, 2, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
19 { V4L2_PIX_FMT_NV16, 1, 2, 1, 1, 2, 2, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
20 { V4L2_PIX_FMT_NV61, 1, 2, 1, 1, 2, 2, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
21 { V4L2_PIX_FMT_NV24, 1, 3, 1, 1, 2, 1, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
[all …]
/linux-6.14.4/include/dt-bindings/pinctrl/
Dpads-imx8qxp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 #define IMX8QXP_PCIE_CTRL0_WAKE_B 2
15 #define IMX8QXP_USB_SS3_TC0 4
190 … IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4
192 … IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4
194 … IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4
197 … IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2
198 … IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4
201 … IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4
204 … IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2
[all …]
Dpads-imx8dxl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define IMX8DXL_PCIE_CTRL0_WAKE_B 2
14 #define IMX8DXL_USB_SS3_TC0 4
149 … IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4
152 … IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4
155 … IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4
159 … IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2
160 … IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4
164 … IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4
168 … IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3568-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 acodec_pins: acodec-pins {
36 /omit-if-no-ref/
37 audiopwm_lout: audiopwm-lout {
40 <1 RK_PA0 4 &pcfg_pull_none>;
43 /omit-if-no-ref/
44 audiopwm_loutn: audiopwm-loutn {
[all …]
/linux-6.14.4/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
68 #define XCHAL_NCP_SA_ALIGN 4
71 #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
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/linux-6.14.4/include/sound/
Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /* MIDI 1.0 / 2.0 Status Code (4bit) */
31 UMP_CC_BREATH = 2,
32 UMP_CC_FOOT = 4,
131 u32 type:4;
132 u32 group:4;
133 u32 status:4;
134 u32 channel:4;
140 u32 channel:4;
141 u32 status:4;
[all …]
/linux-6.14.4/arch/arm64/include/asm/
Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
21 * C5.2, version:ARM DDI 0487A.f)
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
[all …]
/linux-6.14.4/arch/alpha/lib/
Dmemmove.S1 /* SPDX-License-Identifier: GPL-2.0 */
7 * This is hand-massaged output from the original memcpy.c. We defer to
15 .align 4
24 addq $16,$18,$4
26 cmpule $4,$17,$1 /* dest + n <= src */
27 cmpule $5,$16,$2 /* dest >= src + n */
29 bis $1,$2,$1
31 xor $16,$17,$2
34 and $2,7,$2 /* Test for src/dest co-alignment. */
39 and $4,7,$1
[all …]
/linux-6.14.4/arch/m68k/lib/
Dchecksum.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Andreas Schwab, <[email protected]-dortmund.de>
19 * length-counter instead of the length counter
22 * data-registers to hold input values and one tries to
43 * is aligned on either a 2-byte or 4-byte boundary. in csum_partial()
45 __asm__("movel %2,%3\n\t" in csum_partial()
47 "jeq 2f\n\t" in csum_partial()
48 "subql #2,%1\n\t" /* buff%4==2: treat first word */ in csum_partial()
50 "addql #2,%1\n\t" /* len was == 2, treat only rest */ in csum_partial()
51 "jra 4f\n" in csum_partial()
[all …]
/linux-6.14.4/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
66 /* Save area for non-coprocessor optional and custom (TIE) state: */
68 #define XCHAL_NCP_SA_ALIGN 4
71 #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
[all …]
/linux-6.14.4/drivers/media/platform/verisilicon/
Dhantro_vp9.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 u8 sign[2];
11 u8 class0_bit[2][1];
12 u8 fr[2][3];
13 u8 class0_hp[2];
14 u8 hp[2];
15 u8 classes[2][10];
16 u8 class0_fr[2][2][3];
17 u8 bits[2][10];
21 u8 inter_mode[7][4];
[all …]
/linux-6.14.4/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <[email protected]>
9 Version 2 (EeePC) hardware support based on patches
16 2. Extra knobs
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
22 5. Hardware version 2
25 5.2.1 Parity checking and packet re-synchronization
26 5.2.2 One/Three finger touch
32 6.2.2 Two finger touch
[all …]
/linux-6.14.4/arch/arm/crypto/
Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
7 @ Public License version 2 as published by the Free Software Foundation.
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
31 @ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
[all …]
/linux-6.14.4/drivers/media/dvb-frontends/
Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define STV090x_OFFST_MCHIP_IDENT_FIELD 4
15 #define STV090x_WIDTH_MCHIP_IDENT_FIELD 4
17 #define STV090x_WIDTH_MRELEASE_FIELD 4
23 #define STV090x_WIDTH_DACR1_VALUE_FIELD 4
34 #define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4
44 #define STV090x_OFFST_SSTREAM_LCK_3_FIELD 4
48 #define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2
62 #define STV090x_OFFST_SPKTDEL_ERROR_2_FIELD 4
66 #define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2
[all …]
/linux-6.14.4/arch/mips/include/asm/
Dpgtable-32.h19 #include <asm-generic/pgtable-nopmd.h>
26 * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
28 * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
29 * our 2-level table layout would normally have a PGD entry cover a contiguous
30 * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
31 * pointers, each pointing to a 4KB physical page). The problem is that 4MB,
32 * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
33 * support, not one of the standard supported sizes (1MB,4MB,16MB,...).
37 * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
39 * NOTE: We don't yet support huge pages if extended-addressing is enabled
[all …]
/linux-6.14.4/Documentation/userspace-api/media/v4l/
Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
56 noted by the presence of bit 31 in the 4CC value), and on the number of bits
[all …]
Dsubdev-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
17 :widths: 1 1 2
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
[all …]
/linux-6.14.4/arch/xtensa/variants/csp/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
63 /* Save area for non-coprocessor optional and custom (TIE) state: */
65 #define XCHAL_NCP_SA_ALIGN 4
68 #define XCHAL_TOTAL_SA_SIZE 48 /* with 16-byte align padding */
69 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
81 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
82 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
85 * galign = group byte alignment (power of 2) (galign >= align)
86 * align = register byte alignment (power of 2)
[all …]
/linux-6.14.4/tools/testing/selftests/bpf/prog_tests/
Dbtf.c1 /* SPDX-License-Identifier: GPL-2.0 */
100 * int q[4][8];
108 BTF_TYPE_INT_ENC(0, BTF_INT_SIGNED, 0, 32, 4), /* [1] */
110 BTF_TYPE_INT_ENC(0, 0, 0, 64, 8), /* [2] */
114 BTF_TYPE_ARRAY_ENC(1, 1, 8), /* [4] */
117 BTF_MEMBER_ENC(NAME_TBD, 2, 0), /* unsigned long long m;*/
120 BTF_MEMBER_ENC(NAME_TBD, 4, 128),/* int p[8] */
121 BTF_MEMBER_ENC(NAME_TBD, 6, 384),/* int q[4][8] */
124 /* int[4][8] */
125 BTF_TYPE_ARRAY_ENC(4, 1, 4), /* [6] */
[all …]

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