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/linux-6.14.4/Documentation/hwmon/
D	lochnagar.rst	`31 power1_average_interval Power averaging time input valid from 1 to 1708mS 33 in1_input Measured voltage for 1V8 DSP (milliVolts) 34 in1_label "1V8 DSP" 35 curr2_input Measured current for 1V8 DSP (milliAmps) 36 curr2_label "1V8 DSP" 37 power2_average Measured average power for 1V8 DSP (microWatts) 38 power2_average_interval Power averaging time input valid from 1 to 1708mS 39 power2_label "1V8 DSP" 40 in2_input Measured voltage for 1V8 CDC (milliVolts) 41 in2_label "1V8 CDC" [all …]`
/linux-6.14.4/arch/arm64/crypto/
D	sm4-ce-ccm-core.S	`17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31 32 mov vctr.d[1], x8; \ 34 adds x8, x8, #1; \ 72 sub w3, w3, #1 132 inc_le128(v8) /* +0 / 133 inc_le128(v9) / +1 */ 139 SM4_CRYPT_BLK2(v8, RMAC) 140 eor v8.16b, v8.16b, v0.16b 152 st1 {v8.16b-v11.16b}, [x1], #64 164 inc_le128(v8) [all …]`
D	sm4-ce-cipher-core.S	`6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8 19 ld1 {v8.4s}, [x2] 21 CPU_LE( rev32 v8.16b, v8.16b ) 23 sm4e v8.4s, v0.4s 24 sm4e v8.4s, v1.4s 25 sm4e v8.4s, v2.4s 26 sm4e v8.4s, v3.4s 27 sm4e v8.4s, v4.4s 28 sm4e v8.4s, v5.4s 29 sm4e v8.4s, v6.4s [all …]`
D	sm4-ce-core.S	`17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 146 sub w3, w3, #1; 195 sub w4, w4, #1 233 rev32 v8.16b, v0.16b 242 SM4_CRYPT_BLK8_BE(v8, v9, v10, v11, v12, v13, v14, v15) 244 eor v8.16b, v8.16b, RIV.16b 253 st1 {v8.16b-v11.16b}, [x1], #64 270 rev32 v8.16b, v0.16b 275 SM4_CRYPT_BLK4_BE(v8, v9, v10, v11) 277 eor v8.16b, v8.16b, RIV.16b [all …]`
D	sm3-ce-core.S	`12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 45 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s 46 shl \t1\().4s, \t0\().4s, #1 48 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i 63 round \ab, \s0, v12, v11, 1 79 ld1 {v8.4s-v9.4s}, [x0] 80 rev64 v8.4s, v8.4s 82 ext v8.16b, v8.16b, v8.16b, #8 90 sub w2, w2, #1 92 mov v15.16b, v8.16b [all …]`
D	aes-neon.S	`24 tbnz \reg, #1, \lbl 30 shl \out, \in, #1 84 mul_by_x2 v8.16b, \in\().16b, v9.16b, v12.16b 85 eor \in\().16b, \in\().16b, v8.16b 86 rev32 v8.8h, v8.8h 87 eor \in\().16b, \in\().16b, v8.16b 90 mul_by_x v9.16b, \in\().16b, v8.16b, v12.16b 91 rev32 v8.8h, \in\().8h 92 eor v8.16b, v8.16b, v9.16b 93 eor \in\().16b, \in\().16b, v8.16b [all …]`
D	sha3-ce-core.S	`3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions 15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 46 ld1 { v0.1d- v3.1d}, [x0] 47 ld1 { v4.1d- v7.1d}, [x8], #32 48 ld1 { v8.1d-v11.1d}, [x8], #32 49 ld1 {v12.1d-v15.1d}, [x8], #32 50 ld1 {v16.1d-v19.1d}, [x8], #32 51 ld1 {v20.1d-v23.1d}, [x8], #32 52 ld1 {v24.1d}, [x8] 54 0: sub w2, w2, #1 [all …]`
D	aes-neonbs-core.S	`339 \t0, \t1, \t2, \t3, \t4, \t5, \t6, \t7, 1 360 swapmove_2x \x0, \x1, \x2, \x3, 1, \t0, \t2, \t3 361 swapmove_2x \x4, \x5, \x6, \x7, 1, \t0, \t2, \t3 386 ld1 {v17.4s}, [x1], #16 // load round 1 key 388 movi v8.16b, #0x01 // bit masks 398 sub x2, x2, #1 405 cmtst v0.16b, v7.16b, v8.16b 418 subs x2, x2, #1 439 tbl v0.16b, {v10.16b}, v8.16b 441 tbl v1.16b, {v11.16b}, v8.16b [all …]`
D	chacha-neon-core.S	`67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1)) 69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2)) 71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3)) 96 // x1 = shuffle32(x1, MASK(2, 1, 0, 3)) 98 // x2 = shuffle32(x2, MASK(1, 0, 3, 2)) 100 // x3 = shuffle32(x3, MASK(0, 3, 2, 1)) 111 // x1: 1 data block output, o 112 // x2: 1 data block input, i 120 ld1 {v8.4s-v11.4s}, [x0] 127 add v0.4s, v0.4s, v8.4s [all …]`
D	aes-modes.S	`76 subs w4, w4, #1 106 subs w4, w4, #1 163 subs w4, w4, #1 190 ld1 {v4.16b}, [x1], #16 /* get 1 ct block / 198 ld1 {v5.16b}, [x1], #16 / reload 1 ct block / 199 ld1 {cbciv.16b}, [x1], #16 / reload 1 ct block / 211 ld1 {cbciv.16b}, [x1], #16 / reload 1 ct block / 228 subs w4, w4, #1 347 umov IV_PART, vctr.d[1] 360 Set up the counter values in v0-v{MAX_STRIDE-1}. [all …]`
D	sha512-ce-core.S	`3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions 15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19 111 ld1 {v8.2d-v11.2d}, [x0] 120 sub w2, w2, #1 133 mov v0.16b, v8.16b 144 dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17 145 dround 3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18 146 dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19 147 dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12 148 dround 1, 4, 3, 0, 2, 24, 28, 16, 17, 15, 12, 13 [all …]`
/linux-6.14.4/arch/sh/boards/mach-hp6xx/
D	setup.c	`31 [1] = { 44 .id = -1, 51 .id = -1, 57 u8 v8; in dac_audio_start() local 65 v8 = inb(PKDR); in dac_audio_start() 66 v8 &= ~PKDR_SPEAKER; in dac_audio_start() 67 outb(v8, PKDR); in dac_audio_start() 75 u8 v8; in dac_audio_stop() local 83 v8 = inb(PKDR); in dac_audio_stop() 84 v8 \|= PKDR_SPEAKER; in dac_audio_stop() [all …]`
/linux-6.14.4/arch/powerpc/lib/
D	crc32-vpmsum_core.S	`101 vspltisw v0,-1 106 /* Get the initial value into v8 / 107 vxor v8,v8,v8 108 MTVRD(v8, R3) 110 vsldoi v8,zeroes,v8,8 / shift into bottom 32 bits / 112 vsldoi v8,v8,zeroes,4 / shift into top 32 bits */ 127 1: lis r7,MAX_SIZE@h 148 addi r7,r7,-1 172 cmpdi r0,1 195 vxor v16,v16,v8 [all …]`
D	memcpy_power7.S	`11 /* 0 == don't use VMX, 1 == use VMX / 42 bf cr74+3,1f 44 addi r4,r4,1 46 addi r3,r3,1 48 1: bf cr74+2,2f 54 2: bf cr74+1,3f 136 6: bf cr74+1,7f 191 12: bf cr74+1,13f 232 * 1 for the store side. 236 ori r9,r9,1 /* stream=1 */ [all …]`
D	copyuser_power7.S	`11 /* 0 == don't use VMX, 1 == use VMX / 98 bf cr74+3,1f 100 addi r4,r4,1 102 addi r3,r3,1 104 1: bf cr74+2,2f 110 2: bf cr74+1,3f 192 6: bf cr74+1,7f 247 12: bf cr74+1,13f 286 * 1 for the store side. 290 ori r9,r9,1 /* stream=1 */ [all …]`
/linux-6.14.4/Documentation/devicetree/bindings/mmc/
D	nvidia,tegra20-sdhci.yaml	`43 maxItems: 1 46 maxItems: 1 53 minItems: 1 57 minItems: 1 70 maxItems: 1 83 maxItems: 1 112 nvidia,pad-autocal-pull-down-offset-1v8: 117 nvidia,pad-autocal-pull-down-offset-1v8-timeout: 140 nvidia,pad-autocal-pull-up-offset-1v8: 145 nvidia,pad-autocal-pull-up-offset-1v8-timeout: [all …]`
/linux-6.14.4/Documentation/devicetree/bindings/regulator/
D	fixed-regulator.yaml	`61 maxItems: 1 64 maxItems: 1 71 maxItems: 1 78 maxItems: 1 87 maxItems: 1 111 maxItems: 1 125 reg_1v8: regulator-1v8 { 127 regulator-name = "1v8"; 137 reg_1v8_clk: regulator-1v8-clk { 139 regulator-name = "1v8"; [all …]`
/linux-6.14.4/Documentation/devicetree/bindings/arm/
D	arm,coresight-cti.yaml	`31 are implementation defined, except when the CTI is connected to an ARM v8 34 In this case the ARM v8 architecture defines the required signal connections 35 between CTI and the CPU core and ETM if present. In the case of a v8 37 indicate this feature (arm,coresight-cti-v8-arch). 87 - const: arm,coresight-cti-v8-arch 92 maxItems: 1 99 maxItems: 1 114 arm,coresight-cti-v8-arch used. If the associated device has not been 125 const: 1 141 maxItems: 1 [all …]`
/linux-6.14.4/arch/arm64/boot/dts/arm/
D	Makefile	`3 foundation-v8.dtb foundation-v8-psci.dtb \ 4 foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb 7 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb`
/linux-6.14.4/tools/testing/selftests/powerpc/copyloops/
D	memcpy_power7.S	`11 /* 0 == don't use VMX, 1 == use VMX / 42 bf cr74+3,1f 44 addi r4,r4,1 46 addi r3,r3,1 48 1: bf cr74+2,2f 54 2: bf cr74+1,3f 136 6: bf cr74+1,7f 191 12: bf cr74+1,13f 232 * 1 for the store side. 236 ori r9,r9,1 /* stream=1 */ [all …]`
D	copyuser_power7.S	`11 /* 0 == don't use VMX, 1 == use VMX / 98 bf cr74+3,1f 100 addi r4,r4,1 102 addi r3,r3,1 104 1: bf cr74+2,2f 110 2: bf cr74+1,3f 192 6: bf cr74+1,7f 247 12: bf cr74+1,13f 286 * 1 for the store side. 290 ori r9,r9,1 /* stream=1 */ [all …]`
/linux-6.14.4/arch/sparc/math-emu/
D	math_32.c	31 * These are defined in the third layer of macros: op-1.h, op-2.h 33 * of 1,2 and 4 machine words respectively. [For example, on sparc64 35 * constructs in op-1.h, but on sparc32 they use op-2.h definitions.] 47 * SPARC architecture manual V9, and what I really want is V8... 50 * has to be emulated on V8). So I think I'm going to have 86 #define FSQRTQ 0x02b /* v8 / 87 #define FADDQ 0x043 / v8 / 88 #define FSUBQ 0x047 / v8 / 89 #define FMULQ 0x04b / v8 / 90 #define FDIVQ 0x04f / v8 */ [all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/
D	reg_helper.h	`64 REG_SET_N(reg_name, 1, initial_val, \ 116 f5, v5, f6, v6, f7, v7, f8, v8) \ argument 125 FN(reg, f8), v8) 128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \ argument 137 FN(reg, f8), v8, \ 141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ argument 150 FN(reg, f8), v8, \ 205 #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ argument 214 FN(reg_name, f8), v8) 231 REG_UPDATE_N(reg_name, 1, \ [all …]`
/linux-6.14.4/arch/arm64/boot/dts/hisilicon/
D	hi6220-coresight.dtsi	`78 #address-cells = <1>; 89 port@1 { 90 reg = <1>; 147 #address-cells = <1>; 158 port@1 { 159 reg = <1>; 380 compatible = "arm,coresight-cti-v8-arch", 391 /* CTI - CPU-1 */ 393 compatible = "arm,coresight-cti-v8-arch", 406 compatible = "arm,coresight-cti-v8-arch", [all …]`
/linux-6.14.4/drivers/hwtracing/coresight/
D	coresight-cti-platform.c	17 /* Number of CTI signals in the v8 architecturally defined connection / 26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch" 48 return -1; in of_cti_get_cpu_at_node() 53 return -1; in of_cti_get_cpu_at_node() 58 return (cpu < 0) ? -1 : cpu; in of_cti_get_cpu_at_node() 64 return -1; in of_cti_get_cpu_at_node() 78 return -1; in cti_plat_get_cpu_at_node() 170 Create an architecturally defined v8 connection 186 "ARM v8 architectural CTI connection: missing cpu\n"); in cti_plat_create_v8_connections() 191 /* Allocate the v8 cpu connection memory */ in cti_plat_create_v8_connections() [all …]

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