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/linux-6.14.4/drivers/media/platform/verisilicon/
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
Dhantro_g1_mpeg2_dec.c20 #define G1_REG_REFER1_BASE G1_SWREG(15)
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
[all …]
Dhantro_g1_regs.h20 #define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15)
60 #define G1_REG_DEC_CTRL0_DEC_OUT_DIS BIT(15)
98 #define G1_REG_DEC_CTRL2_TRANSACFRM(x) (((x) & 0x3) << 15)
208 #define G1_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15)
221 #define G1_REG_DEC_CTRL7_PINIT_RLIST_F13(x) (((x) & 0x1f) << 15)
262 #define G1_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 15)
280 #define G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 15)
286 #define G1_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 15)
313 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
314 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
[all …]
Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
/linux-6.14.4/lib/crypto/
Dblake2s-generic.c20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
28 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
29 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/linux-6.14.4/crypto/
Dblake2b_generic.c26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
32 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
33 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
34 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
35 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/linux-6.14.4/arch/arm/crypto/
Dblake2s-core.S113 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
115 // spilling v[8..9], then to v[9..15], then to the message block. r10-r12 and
132 // (v[0], v[4], v[8], v[12]) and (v[1], v[5], v[9], v[13]).
133 __ldrd r10, r11, sp, 16 // load v[12] and v[13]
140 // (v[2], v[6], v[10], v[14]) and (v[3], v[7], v[11], v[15]).
141 __ldrd r8, r9, sp, 8 // load v[10] and v[11]
142 __ldrd r10, r11, sp, 24 // load v[14] and v[15]
145 str r10, [sp, #24] // store v[14]
146 // v[10], v[11], and v[15] are used below, so no need to store them yet.
152 // (v[0], v[5], v[10], v[15]) and (v[1], v[6], v[11], v[12]).
[all …]
Dblake2b-neon-core.S63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
73 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
74 // (v[2], v[6], v[10], v[14]), and (v[3], v[7], v[11], v[15]).
145 // (v[0], v[5], v[10], v[15]), (v[1], v[6], v[11], v[12]),
146 // (v[2], v[7], v[8], v[13]), and (v[3], v[4], v[9], v[14]).
274 // 'v'. Fortunately, there are exactly enough NEON registers to fit the
275 // entire state matrix in q0-q7 and the entire message block in q8-15.
285 veor q6, q6, q14 // v[12..13] = IV[4..5] ^ t[0..1]
287 veor q7, q7, q15 // v[14..15] = IV[6..7] ^ f[0..1]
295 _blake2b_round 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
[all …]
/linux-6.14.4/drivers/gpu/drm/exynos/
Dregs-scaler.h56 * 1 70 74 78 7c 150 154 158 15c
158 #define SCALER_INT_EN_ILLEGAL_DST_CB_BASE (1 << 15)
186 #define SCALER_INT_STATUS_ILLEGAL_DST_CB_BASE (1 << 15)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
222 #define SCALER_L8 15
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
239 #define SCALER_SRC_Y_POS_GET_YV_POS(r) SCALER_GET(r, 15, 0)
[all …]
/linux-6.14.4/drivers/video/fbdev/
Datafb_iplan2p8.c53 if (!((sx ^ dx) & 15)) { in atafb_iplan2p8_copyarea()
57 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
58 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
59 if (sx & 15) { in atafb_iplan2p8_copyarea()
78 if (width & 15) in atafb_iplan2p8_copyarea()
82 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
83 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p8_copyarea()
85 if ((sx + width) & 15) { in atafb_iplan2p8_copyarea()
104 if (sx & 15) in atafb_iplan2p8_copyarea()
113 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
[all …]
Datafb_iplan2p4.c46 if (!((sx ^ dx) & 15)) { in atafb_iplan2p4_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
52 if (sx & 15) { in atafb_iplan2p4_copyarea()
71 if (width & 15) in atafb_iplan2p4_copyarea()
75 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
76 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p4_copyarea()
78 if ((sx + width) & 15) { in atafb_iplan2p4_copyarea()
97 if (sx & 15) in atafb_iplan2p4_copyarea()
106 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local
[all …]
Dvalkyriefb.h8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
101 15,
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
107 /* Register values for 1024x768, 72Hz mode (15) */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
110 * caused the 15" Apple Studio Display to not work in this mode. While this
117 15,
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
119 /* I interpolated the V=69.71 from the vmode 14 and old 15
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
[all …]
Datafb_iplan2p2.c46 if (!((sx ^ dx) & 15)) { in atafb_iplan2p2_copyarea()
50 src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
51 dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
52 if (sx & 15) { in atafb_iplan2p2_copyarea()
71 if (width & 15) in atafb_iplan2p2_copyarea()
75 src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
76 dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL); in atafb_iplan2p2_copyarea()
78 if ((sx + width) & 15) { in atafb_iplan2p2_copyarea()
97 if (sx & 15) in atafb_iplan2p2_copyarea()
106 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local
[all …]
/linux-6.14.4/arch/arm64/crypto/
Dsha512-ce-core.S15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
94 sha512su0 v\in0\().2d, v\in1\().2d
98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
100 add v\i4\().2d, v\i1\().2d, v\i3\().2d
[all …]
/linux-6.14.4/drivers/net/ethernet/altera/
Daltera_msgdmahw.h19 * bit 15:0 sequence number
22 * bit 15:0 read stride
39 #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
81 * bit 15:0 - read fill level
83 u32 resp_fill_level; /* bit 15:0 */
85 * bit 15:0 - read sequence number
105 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) argument
106 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1) argument
107 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2) argument
108 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3) argument
[all …]
Daltera_tse.h53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
72 #define MAC_CMDCFG_LOOP_ENA BIT(15)
73 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) argument
85 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) argument
86 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) argument
87 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) argument
88 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) argument
89 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) argument
90 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) argument
91 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) argument
[all …]
/linux-6.14.4/arch/alpha/kernel/
Dentry.S41 * regs 9-15 preserved by C code
157 .cfi_rel_offset $15, 48
168 .cfi_restore $15
196 /* save $9 - $15 so the inline exception code can manipulate them. */
205 stq $15, 48($sp)
212 .cfi_rel_offset $15, 48
225 ldq $15, 48($sp)
233 .cfi_restore $15
271 stq $15, 120($sp)
299 .cfi_rel_offset $15, 15*8
[all …]
/linux-6.14.4/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
64 #define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s) SHIFT_AND_MASK_BITS(s, 15, 0)
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
[all …]
/linux-6.14.4/arch/x86/include/asm/
Dperf_event_p4.h40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
62 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) argument
63 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) argument
81 #define p4_config_pack_escr(v) (((u64)(v)) << 32) argument
82 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
83 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) argument
84 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) argument
86 #define p4_config_unpack_emask(v) \ argument
[all …]
/linux-6.14.4/arch/s390/include/asm/
Dfpu-insn-asm.h76 \opd = 15
140 \opd = 15
203 * are stored in instruction bits 12-15.
274 .word (0xE700 | ((v1&15) << 4))
286 .macro VLVG v, gr, disp, m
287 VX_NUM v1, \v
290 .word 0xE700 | ((v1&15) << 4) | r3
294 .macro VLVGB v, gr, index, base
295 VLVG \v, \gr, \index, \base, 0
297 .macro VLVGH v, gr, index
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/sound/
Dadi,max98396.yaml13 The MAX98396 is a mono Class-DG speaker amplifier with I/V sense.
28 description: A 1.8V supply that powers up the AVDD pin.
31 description: A 1.2V supply that powers up the DVDD pin.
34 description: A 1.2V or 1.8V supply that powers up the VDDIO pin.
37 description: A 3.0V to 20V supply that powers up the PVDD pin.
40 description: A 3.3V to 5.5V supply that powers up the VBAT pin.
46 maximum: 15
53 maximum: 15
60 maximum: 15
69 maximum: 15
[all …]
/linux-6.14.4/sound/ppc/
Dsnd_ps3_reg.h72 31 24 23 16 15 8 7 0
95 31 24 23 16 15 8 7 0
105 31 24 23 16 15 8 7 0
124 31 24 23 16 15 8 7 0
149 #define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */
154 31 24 23 16 15 8 7 0
184 31 24 23 16 15 8 7 0
224 31 24 23 16 15 8 7 0
235 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */
236 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */
[all …]
/linux-6.14.4/lib/
Dbitfield_kunit.c11 #define CHECK_ENC_GET_U(tp, v, field, res) do { \ argument
15 _res = u##tp##_encode_bits(v, field); \
17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
20 u##tp##_get_bits(_res, field) != v); \
24 #define CHECK_ENC_GET_LE(tp, v, field, res) do { \ argument
28 _res = le##tp##_encode_bits(v, field); \
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
35 le##tp##_get_bits(_res, field) != v);\
39 #define CHECK_ENC_GET_BE(tp, v, field, res) do { \ argument
43 _res = be##tp##_encode_bits(v, field); \
[all …]
/linux-6.14.4/drivers/iio/adc/
Dstm32-dfsdm.h52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) argument
54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) argument
56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) argument
58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) argument
60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) argument
62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) argument
64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) argument
65 #define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) argument
68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) argument
[all …]
/linux-6.14.4/fs/smb/client/compress/
Dlz77.c22 #define LZ77_HASH_LOG 15
36 static __always_inline void lz77_write8(u8 *ptr, u8 v) in lz77_write8() argument
38 put_unaligned(v, ptr); in lz77_write8()
41 static __always_inline void lz77_write16(u16 *ptr, u16 v) in lz77_write16() argument
43 put_unaligned_le16(v, ptr); in lz77_write16()
46 static __always_inline void lz77_write32(u32 *ptr, u32 v) in lz77_write32() argument
48 put_unaligned_le32(v, ptr); in lz77_write32()
96 lz77_write8(dst, umin(len, 15)); in lz77_write_match()
102 lz77_write8(b, *b | umin(len, 15) << 4); in lz77_write_match()
106 if (len < 15) in lz77_write_match()
[all …]

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