Searched +full:10 +full:g +full:- +full:usgmii (Results 1 – 3 of 3) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/phy/ |
| D | microchip,sparx5-serdes.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Daniel Machon <[email protected]>
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
23 * Adjustable tx de-emphasis (FFE)
32 The SERDES6G is a high-speed SERDES interface, which can operate at
35 * 100 Mbps (100BASE-FX)
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| /linux-6.14.4/Documentation/networking/ |
| D | phy.rst | 26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
98 receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
126 * Modifying the PCB design to include a fixed delay (e.g: using a specifically
130 -----------------------------------------
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| /linux-6.14.4/drivers/net/phy/ |
| D | phylink.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
44 * struct phylink - internal data type for phylink
61 u8 link_port; /* The current non-phy ethtool port */
103 if ((pl)->config->type == PHYLINK_NETDEV) \
104 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
105 else if ((pl)->config->type == PHYLINK_DEV) \
106 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
118 if ((pl)->config->type == PHYLINK_NETDEV) \
119 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
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