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/linux-6.14.4/Documentation/networking/dsa/
Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <[email protected]>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <[email protected]>
11 - Robert Marko <[email protected]>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <[email protected]>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
21 The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
34 nvmem-cells:
40 nvmem-cell-names:
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Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <[email protected]>
11 - Florian Fainelli <[email protected]>
12 - Heiner Kallweit <[email protected]>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <[email protected]>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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/linux-6.14.4/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
46 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
47 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 * Lanes B-D are numbered 134-136. */
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/linux-6.14.4/drivers/net/dsa/sja1105/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 This is the driver for the NXP SJA1105 (5-port) and SJA1110 (10-port)
15 - SJA1105E (Gen. 1, No TT-Ethernet)
16 - SJA1105T (Gen. 1, TT-Ethernet)
17 - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
18 - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
19 - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
20 - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
21 - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)
22 - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)
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/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <[email protected]>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
25 - nxp,sja1105r
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/linux-6.14.4/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <[email protected]>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <[email protected]>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
25 #define SPEED_100 100
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Daniel Machon <[email protected]>
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
23 * Adjustable tx de-emphasis (FFE)
24 * Tx output amplitude control
32 The SERDES6G is a high-speed SERDES interface, which can operate at
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/linux-6.14.4/Documentation/networking/device_drivers/ethernet/3com/
Dvortex.rst1 .. SPDX-License-Identifier: GPL-2.0
20 - Andrew Morton
21 - Netdev mailing list <[email protected]>
22 - Linux kernel mailing list <linux-[email protected]>
28 Since kernel 2.3.99-pre6, this driver incorporates the support for the
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
33 - 3c590 Vortex 10Mbps
34 - 3c592 EISA 10Mbps Demon/Vortex
35 - 3c597 EISA Fast Demon/Vortex
36 - 3c595 Vortex 100baseTx
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/linux-6.14.4/net/ethtool/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
20 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
22 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
23 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
25 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
26 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
27 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
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/linux-6.14.4/drivers/phy/freescale/
Dphy-fsl-imx8mq-usb.c1 // SPDX-License-Identifier: GPL-2.0+
56 void __iomem *base; member
71 return DIV_ROUND_CLOSEST(percent - 94U, 2); in phy_tx_vref_tune_from_property()
81 case 100 ... 101: in phy_tx_rise_tune_from_property()
135 percent = min(percent, 100U); in phy_pcs_tx_swing_full_from_property()
137 return (percent * 127) / 100; in phy_pcs_tx_swing_full_from_property()
142 struct device *dev = imx_phy->phy->dev.parent; in imx8m_get_phy_tuning_data()
144 if (device_property_read_u32(dev, "fsl,phy-tx-vref-tune-percent", in imx8m_get_phy_tuning_data()
145 &imx_phy->tx_vref_tune)) in imx8m_get_phy_tuning_data()
146 imx_phy->tx_vref_tune = PHY_TUNE_DEFAULT; in imx8m_get_phy_tuning_data()
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/linux-6.14.4/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
23 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
57 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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/linux-6.14.4/drivers/net/ethernet/intel/e1000/
De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
131 e1000_igp_cable_length_100 = 100,
422 /* MAC decode size is 128K - This is the size of BAR0 */
433 #define SPEED_100 100
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
529 /* Receive Descriptor - Packet Split */
553 __le16 length[3]; /* length of buffers 1-3 */
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/linux-6.14.4/drivers/net/ethernet/intel/igb/
De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
188 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
245 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
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/linux-6.14.4/drivers/phy/
Dphy-airoha-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "phy-airoha-pcie-regs.h"
21 /* PCIe-PHY initialization time in ms needed by the hw to complete */
31 * struct airoha_pcie_phy - PCIe phy driver main structure
34 * @csr_2l: Analogic lane IO mapped register base address
35 * @pma0: IO mapped register base address of PMA0-PCIe
36 * @pma1: IO mapped register base address of PMA1-PCIe
37 * @p0_xr_dtime: IO mapped register base address of port0 Tx-Rx detection time
38 * @p1_xr_dtime: IO mapped register base address of port1 Tx-Rx detection time
39 * @rx_aeq: IO mapped register base address of Rx AEQ training
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/linux-6.14.4/drivers/net/phy/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
64 Currently tested with mpc866ads and mpc8349e-mitx.
104 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
105 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
113 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
127 Currently supports the Asix Electronics PHY found in the X-Surf 100
136 found in the X-Surf 100 AX88796B package.
252 Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
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/linux-6.14.4/Documentation/networking/device_drivers/ethernet/intel/
De100.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Base Driver for the Intel(R) PRO/100 Family of Adapters
12 - In This Release
13 - Identifying Your Adapter
14 - Building and Installation
15 - Driver Configuration Parameters
16 - Additional Configurations
17 - Known Issues
18 - Support
24 This file describes the Linux Base Driver for the Intel(R) PRO/100 Family of
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/linux-6.14.4/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
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/linux-6.14.4/Documentation/networking/device_drivers/ethernet/ti/
Dtlan.rst1 .. SPDX-License-Identifier: GPL-2.0
9 (C) 1997-1998 Caldera, Inc.
13 (C) 1999-2001 Torben Mathiasen <[email protected], [email protected]>
31 0e11 ae32 Compaq Netelligent 10/100 TX PCI UTP
34 0e11 ae40 Compaq Netelligent Dual 10/100 TX PCI UTP
35 0e11 ae43 Compaq Netelligent Integrated 10/100 TX UTP
36 0e11 b011 Compaq Netelligent 10/100 TX Embedded UTP
38 0e11 b030 Compaq Netelligent 10/100 TX UTP
41 108d 0012 Olicom OC-2325
42 108d 0013 Olicom OC-2183
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/linux-6.14.4/drivers/gpu/drm/sun4i/
Dsun4i_hdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
28 * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz in fifo_transfer()
29 * clock. As clock rate is fixed, just round it up to 100 us. in fifo_transfer()
31 const unsigned long byte_time_ns = 100; in fifo_transfer()
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
45 * For TX the threshold is for an empty FIFO. in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
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/linux-6.14.4/arch/arm/boot/dts/nxp/vf/
Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
26 led-debug {
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/linux-6.14.4/drivers/atm/
Deni.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */
4 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
28 #define TX_DMA_BUF 100 /* should be enough for 64 kB */
33 #define ENI_ZEROES_SIZE 4 /* need that many DMA-able zero bytes */
42 void __iomem *send; /* base, 0 if unused */
45 unsigned long tx_pos; /* current TX write position */
46 unsigned long words; /* size of TX queue */
47 int index; /* TX channel number */
50 struct sk_buff_head backlog; /* queue of waiting TX buffers */
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