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/linux-6.14.4/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
46 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
47 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 * Lanes B-D are numbered 134-136. */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <[email protected]>
11 - Daniel Machon <[email protected]>
22 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
23 * Adjustable tx de-emphasis (FFE)
32 The SERDES6G is a high-speed SERDES interface, which can operate at
35 * 100 Mbps (100BASE-FX)
[all …]
/linux-6.14.4/drivers/net/ethernet/chelsio/cxgb/
Dmv88e1xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MII_GBCR 9 /* 1000Base-T control register */
19 #define MII_GBSR 10 /* 1000Base-T status register */
21 /* 1000Base-T control register fields */
28 /* 1000Base-T status register fields */
72 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) argument
73 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) argument
81 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) argument
82 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) argument
108 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) argument
[all …]
/linux-6.14.4/drivers/net/ethernet/ti/
Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-[email protected]>
8 * Wingman Kwok <w-[email protected]>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100) argument
23 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x))) argument
26 #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004) argument
27 #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010) argument
28 #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014) argument
29 #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018) argument
31 static void sgmii_write_reg(void __iomem *base, int reg, u32 val) in sgmii_write_reg() argument
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <[email protected]>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
Ddcn35_smu.c51 #define BASE(seg) BASE_INNER(seg) macro
53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
61 CTX->logger
90 …e conditions for turning SLDO2 on/off . bit[0]==1 precondition is met, bit[1-2] are for DPPHY numb…
124 if (delay_us >= 1000) in dcn35_smu_wait_for_response()
125 msleep(delay_us/1000); in dcn35_smu_wait_for_response()
129 if (clk_mgr->base.ctx->dc->debug.disable_timeout) in dcn35_smu_wait_for_response()
131 } while (max_retries--); in dcn35_smu_wait_for_response()
149 return -1; in dcn35_smu_send_msg_with_param()
171 return -1; in dcn35_smu_send_msg_with_param()
[all …]
/linux-6.14.4/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
24 #include "cpufreq-dt.h"
64 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) argument
73 #define MIN_VOLT_MV 1000
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
132 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, in armada37xx_cpufreq_dvfs_setup() argument
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/vf/
Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
26 led-debug {
[all …]
/linux-6.14.4/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <[email protected]>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <[email protected]>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
26 #define SPEED_1000 1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
[all …]
/linux-6.14.4/drivers/pwm/
Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0) argument
19 #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4) argument
20 #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8) argument
21 #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC) argument
37 void __iomem *base; member
70 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, in hibvt_pwm_set_bits() argument
73 void __iomem *address = base + offset; in hibvt_pwm_set_bits()
86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
[all …]
/linux-6.14.4/drivers/net/phy/
Dsfp-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * struct sfp_bus - internal representation of a sfp bus
36 * sfp_parse_port() - Parse the EEPROM base ID, setting the port type
43 * %PORT_TP, %PORT_FIBRE or %PORT_OTHER. If @support is non-%NULL,
55 switch (id->base.connector) { in sfp_parse_port()
76 if (id->base.e1000_base_t) { in sfp_parse_port()
88 dev_warn(bus->sfp_dev, "SFP: unknown connector id 0x%02x\n", in sfp_parse_port()
89 id->base.connector); in sfp_parse_port()
111 * sfp_may_have_phy() - indicate whether the module may have a PHY
120 if (id->base.e1000_base_t) in sfp_may_have_phy()
[all …]
Dmarvell-88x2222.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 88x2222 dual-port multi-speed ethernet transceiver.
7 * 1000Base-X or 10GBase-R on the line side.
8 * SGMII over 1000Base-X.
36 /* 1000Base-X/SGMII Control Register */
39 /* 1000BASE-X/SGMII Status Register */
42 /* 1000Base-X Auto-Negotiation Advertisement Register */
45 /* 1000Base-X PHY Specific Status Register */
110 struct mv2222_data *priv = phydev->priv; in mv2222_set_sgmii_speed()
112 switch (phydev->speed) { in mv2222_set_sgmii_speed()
[all …]
/linux-6.14.4/drivers/gpu/drm/arm/display/komeda/
Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
30 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
31 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
34 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
35 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
53 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
54 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
58 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
61 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
65 * komeda_crtc_atomic_check - build display output data flow
[all …]
/linux-6.14.4/drivers/scsi/pcmcia/
Dnsp_cs.c3 NinjaSCSI-3 / NinjaSCSI-32Bi PCMCIA SCSI host adapter card driver
21 I-O DATA PCSC-F (Workbit NinjaSCSI-3)
22 "WBT", "NinjaSCSI-3", "R1.0"
23 I-O DATA CBSC-II (Workbit NinjaSCSI-32Bi in 16bit mode)
56 MODULE_DESCRIPTION("WorkBit NinjaSCSI-3 / NinjaSCSI-32Bi(16bit) PCMCIA SCSI host adapter module");
81 .name = "WorkBit NinjaSCSI-3/32Bi(16bit)",
90 .dma_boundary = PAGE_SIZE - 1,
94 static nsp_hw_data nsp_data_base; /* attach <-> detect glue */
169 printk("nsp_cs-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); in nsp_cs_dmessage()
178 * You must be set SCpnt->result before call this function.
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/
Di915_utils.h43 #define FDO_BUG_URL "https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html"
45 #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ argument
46 __stringify(x), (long)(x))
63 #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV)
67 drm_dbg(&(i915)->drm, fmt, ##__VA_ARGS__); \
69 drm_err(&(i915)->drm, fmt, ##__VA_ARGS__); \
78 start__ >= max__ || size__ > max__ - start__; \
90 start__ > max__ || size__ > max__ - start__; \
98 (typeof(ptr))(__v & -BIT(n)); \
101 #define ptr_unmask_bits(ptr, n) ((unsigned long)(ptr) & (BIT(n) - 1))
[all …]
/linux-6.14.4/drivers/gpu/drm/radeon/
Drs690.c42 for (i = 0; i < rdev->usec_timeout; i++) { in rs690_mc_wait_for_idle()
49 return -1; in rs690_mc_wait_for_idle()
74 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, in rs690_pm_info()
76 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); in rs690_pm_info()
82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); in rs690_pm_info()
83 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); in rs690_pm_info()
84 if (le16_to_cpu(info->info.usK8MemoryClock)) in rs690_pm_info()
85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); in rs690_pm_info()
86 else if (rdev->clock.default_mclk) { in rs690_pm_info()
87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); in rs690_pm_info()
[all …]
/linux-6.14.4/drivers/gpu/drm/sprd/
Dsprd_dsi.c1 // SPDX-License-Identifier: GPL-2.0
139 return (readl(ctx->base + offset) & mask) >> shift; in dsi_reg_rd()
148 ret = readl(ctx->base + offset); in dsi_reg_wr()
151 writel(ret, ctx->base + offset); in dsi_reg_wr()
158 u32 ret = readl(ctx->base + offset); in dsi_reg_up()
160 writel((ret & ~mask) | (val & mask), ctx->base + offset); in dsi_reg_up()
166 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_write()
169 return -EINVAL; in regmap_tst_io_write()
171 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); in regmap_tst_io_write()
188 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_read()
[all …]
/linux-6.14.4/drivers/i2c/busses/
Di2c-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-mt7621.c
9 * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
48 #define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK) argument
58 #define TIMEOUT_MS 1000
61 void __iomem *base; member
75 ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG, in mtk_i2c_wait_idle()
77 10, TIMEOUT_MS * 1000); in mtk_i2c_wait_idle()
79 dev_dbg(i2c->dev, "idle err(%d)\n", ret); in mtk_i2c_wait_idle()
88 ret = device_reset(i2c->adap.dev.parent); in mtk_i2c_reset()
[all …]
Di2c-highlander.c1 // SPDX-License-Identifier: GPL-2.0
42 void __iomem *base; member
52 static int iic_timeout = 1000, iic_read_delay;
56 iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR); in highlander_i2c_irq_enable()
61 iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR); in highlander_i2c_irq_disable()
66 iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR); in highlander_i2c_start()
71 iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR); in highlander_i2c_done()
78 smmr = ioread16(dev->base + SMMR); in highlander_i2c_setup()
86 iowrite16(smmr, dev->base + SMMR); in highlander_i2c_setup()
91 for (; len > 1; len -= 2) { in smbus_write_data()
[all …]
/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dauxg94.c24 #define g94_i2c_aux(p) container_of((p), struct g94_i2c_aux, base)
28 struct nvkm_i2c_aux base; member
35 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in g94_i2c_aux_fini()
36 nvkm_mask(device, 0x00e4e4 + (aux->ch * 0x50), 0x00310000, 0x00000000); in g94_i2c_aux_fini()
42 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in g94_i2c_aux_init()
49 timeout = 1000; in g94_i2c_aux_init()
51 ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50)); in g94_i2c_aux_init()
53 if (!timeout--) { in g94_i2c_aux_init()
54 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); in g94_i2c_aux_init()
55 return -EBUSY; in g94_i2c_aux_init()
[all …]
Dauxgm200.c24 #define gm200_i2c_aux(p) container_of((p), struct gm200_i2c_aux, base)
28 struct nvkm_i2c_aux base; member
35 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in gm200_i2c_aux_fini()
36 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000); in gm200_i2c_aux_fini()
42 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in gm200_i2c_aux_init()
49 timeout = 1000; in gm200_i2c_aux_init()
51 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); in gm200_i2c_aux_init()
53 if (!timeout--) { in gm200_i2c_aux_init()
54 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); in gm200_i2c_aux_init()
55 return -EBUSY; in gm200_i2c_aux_init()
[all …]
/linux-6.14.4/Documentation/admin-guide/pm/
Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
[all …]
/linux-6.14.4/drivers/staging/sm750fb/
Dsm750.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define MHZ(x) ((x) * 1000000) argument
52 /* base virtual address of DPR registers */
54 /* base virtual address of de data port */
63 u32 base, u32 pitch, u32 bpp,
64 u32 x, u32 y, u32 width, u32 height,
127 /* base virtual address and offset of cursor image */
142 /* below attributes belong to info->fix, their value depends on specific adaptor*/
169 * output->channel ==> &crtc->channel
188 unsigned long long numerator = 1000 * 1000 * 1000 * 1000ULL; in ps_to_hz()

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