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/linux-6.14.4/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
51 #define BMCR_RESET 0x8000 /* Reset to default state */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
[all …]
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
46 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
47 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 * Lanes B-D are numbered 134-136. */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <[email protected]>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <[email protected]>
11 - Robert Marko <[email protected]>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
19 MAC, while second one is SGMII for connection to MAC or fiber.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
[all …]
Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <[email protected]>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
[all …]
/linux-6.14.4/include/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
65 * The one exception to IEEE 802.3u is that 100baseT4 is placed
66 * between 100T-full and 100T-half. If your phy does not support
68 * priority order, you will need to roll your own function.
90 * @duplex_lock: Non-zero if duplex is locked at full
112 * settings to phy autonegotiation advertisements for the
140 * settings to phy autonegotiation advertisements for the
168 * to ethtool advertisement settings.
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/
Di915_utils.h4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43 #define FDO_BUG_URL "https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html"
45 #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ argument
46 __stringify(x), (long)(x))
63 #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV)
[all …]
/linux-6.14.4/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
24 #include "cpufreq-dt.h"
64 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) argument
73 #define MIN_VOLT_MV 1000
107 * unstable because we do not know how to configure it properly.
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
[all …]
/linux-6.14.4/drivers/gpu/drm/arm/display/komeda/
Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
30 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
31 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
34 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
35 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
41 /* connector doesn't config any color_format, use RGB444 as default */ in komeda_crtc_get_color_config()
53 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
54 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
58 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
61 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
[all …]
/linux-6.14.4/arch/mips/alchemy/common/
Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
8 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
43 #define USBCFG_FLA(x) (((x) & 0x3f) << 8) argument
74 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
75 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
76 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
[all …]
/linux-6.14.4/drivers/memory/
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <[email protected]>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
97 * The first 1MB of GPMC address space is typically mapped to
98 * the internal ROM. Never allocate the first page, to
99 * facilitate bug detection; even if we didn't boot from ROM.
207 /* Structure to save gpmc cs context */
[all …]
/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgt215.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
Ddcn35_smu.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
51 #define BASE(seg) BASE_INNER(seg) macro
53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
61 CTX->logger
75 …SSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC //To ask PMFW turn off TMDP 48MHz refclk during displa…
[all …]
/linux-6.14.4/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
59 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
[all …]
/linux-6.14.4/drivers/net/phy/
Dsfp-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * struct sfp_bus - internal representation of a sfp bus
36 * sfp_parse_port() - Parse the EEPROM base ID, setting the port type
37 * @bus: a pointer to the &struct sfp_bus structure for the sfp module
38 * @id: a pointer to the module's &struct sfp_eeprom_id
39 * @support: optional pointer to an array of unsigned long for the
43 * %PORT_TP, %PORT_FIBRE or %PORT_OTHER. If @support is non-%NULL,
55 switch (id->base.connector) { in sfp_parse_port()
76 if (id->base.e1000_base_t) { in sfp_parse_port()
88 dev_warn(bus->sfp_dev, "SFP: unknown connector id 0x%02x\n", in sfp_parse_port()
[all …]
Dsfp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/mdio/mdio-i2c.h>
150 "mod-def0",
152 "tx-fault",
153 "tx-disable",
154 "rate-select0",
155 "rate-select1",
167 /* t_start_up (SFF-8431) or t_init (SFF-8472) is the time required for a
168 * non-cooled module to initialise its laser safety circuitry. We wait
169 * an initial T_WAIT period before we check the tx fault to give any PHY
[all …]
/linux-6.14.4/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
[all …]
/linux-6.14.4/drivers/leds/
Dleds-lm3533.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * leds-lm3533.c -- LM3533 LED driver
5 * Copyright (C) 2011-2012 Texas Instruments
61 return led->id + 2; in lm3533_led_get_ctrlbank_id()
64 static inline u8 lm3533_led_get_lv_reg(struct lm3533_led *led, u8 base) in lm3533_led_get_lv_reg() argument
66 return base + led->id; in lm3533_led_get_lv_reg()
71 return led->id; in lm3533_led_get_pattern()
75 u8 base) in lm3533_led_get_pattern_reg() argument
77 return base + lm3533_led_get_pattern(led) * LM3533_REG_PATTERN_STEP; in lm3533_led_get_pattern_reg()
88 dev_dbg(led->cdev.dev, "%s - %d\n", __func__, enable); in lm3533_led_pattern_enable()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_clk_mgr_smu_msg.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46 * Function to be used instead of REG_WAIT macro because the wait ends when
47 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
48 * won't work with REG_WAIT.
60 if (delay_us >= 1000) in dcn32_smu_wait_for_response()
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
[all …]
/linux-6.14.4/sound/core/seq/
Dseq_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 1998-1999 by Frank van de Pol <[email protected]>
17 #define DEFAULT_FREQUENCY 1000
24 tmr->tempo_base == 1000 ? 1000000 : 10000; in snd_seq_timer_set_tick_resolution()
26 if (tmr->tempo < threshold) in snd_seq_timer_set_tick_resolution()
27 tmr->tick.resolution = (tmr->tempo * tmr->tempo_base) / tmr->ppq; in snd_seq_timer_set_tick_resolution()
31 s = tmr->tempo % tmr->ppq; in snd_seq_timer_set_tick_resolution()
32 s = (s * tmr->tempo_base) / tmr->ppq; in snd_seq_timer_set_tick_resolution()
33 tmr->tick.resolution = (tmr->tempo / tmr->ppq) * tmr->tempo_base; in snd_seq_timer_set_tick_resolution()
34 tmr->tick.resolution += s; in snd_seq_timer_set_tick_resolution()
[all …]
/linux-6.14.4/drivers/regulator/
Dtwl-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * twl-regulator.c -- support regulators in twl4030/twl6030 family chips
25 * These chips are often used in OMAP-based systems.
27 * This driver implements software-based resource control for various
34 u8 base; member
39 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
57 /* LDO control registers ... offset is from the base of its register bank.
58 * The first three registers of all power resource banks help hardware to
81 &value, info->base + offset); in twlreg_read()
90 value, info->base + offset); in twlreg_write()
[all …]
/linux-6.14.4/drivers/i2c/busses/
Di2c-highlander.c1 // SPDX-License-Identifier: GPL-2.0
42 void __iomem *base; member
52 static int iic_timeout = 1000, iic_read_delay;
56 iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR); in highlander_i2c_irq_enable()
61 iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR); in highlander_i2c_irq_disable()
66 iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR); in highlander_i2c_start()
71 iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR); in highlander_i2c_done()
78 smmr = ioread16(dev->base + SMMR); in highlander_i2c_setup()
86 iowrite16(smmr, dev->base + SMMR); in highlander_i2c_setup()
91 for (; len > 1; len -= 2) { in smbus_write_data()
[all …]
Di2c-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-mt7621.c
9 * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
48 #define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK) argument
57 /* timeout waiting for I2C devices to respond */
58 #define TIMEOUT_MS 1000
61 void __iomem *base; member
75 ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG, in mtk_i2c_wait_idle()
77 10, TIMEOUT_MS * 1000); in mtk_i2c_wait_idle()
79 dev_dbg(i2c->dev, "idle err(%d)\n", ret); in mtk_i2c_wait_idle()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Ddcn301_smu.c4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
48 CTX->logger
76 * Function to be used instead of REG_WAIT macro because the wait ends when
77 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
78 * won't work with REG_WAIT.
[all …]

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