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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drockchip,inno-usb2phy.yaml7 title: Rockchip USB2.0 phy with inno IP block
35 const: 0
87 const: 0
110 const: 0
225 reg = <0xe450 0x10>;
229 #clock-cells = <0>;
232 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
234 #phy-cells = <0>;
238 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
239 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
[all …]
/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-inno-usb2.c3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
43 PHY_STATE_HS_ONLINE = 0,
62 USB_CHG_STATE_UNDEFINED = 0,
228 * struct rockchip_usb2phy - usb2.0 phy driver data.
312 return 0; in rockchip_usb2phy_reset()
339 return 0; in rockchip_usb2phy_clk480m_prepare()
391 int ret = 0; in rockchip_usb2phy_clk480m_register()
393 init.flags = 0; in rockchip_usb2phy_clk480m_register()
400 for (i = 0; i < rphy->num_clks; i++) { in rockchip_usb2phy_clk480m_register()
413 init.num_parents = 0; in rockchip_usb2phy_clk480m_register()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml60 description: Use rockchip,rk3588-vo{0,1}-grf instead.
205 "^phy@[0-9a-f]+$":
250 "usb2phy@[0-9a-f]+$":
312 reg = <0xff770000 0x10000>;
323 #phy-cells = <0>;
328 reg = <0xf780 0x20>;
332 #phy-cells = <0>;
337 reg = <0xe450 0x10>;
340 #clock-cells = <0>;
344 #phy-cells = <0>;
[all …]
/linux-6.14.4/drivers/mfd/
Dintel-lpss-pci.c29 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1182),
34 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1237),
39 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x51fb, 0x1028, 0x0beb),
58 if (ret < 0) in intel_lpss_pci_probe()
66 info->mem = pci_resource_n(pdev, 0); in intel_lpss_pci_probe()
67 info->irq = pci_irq_vector(pdev, 0); in intel_lpss_pci_probe()
73 pdev->d3cold_delay = 0; in intel_lpss_pci_probe()
86 return 0; in intel_lpss_pci_probe()
250 { PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info },
251 { PCI_VDEVICE(INTEL, 0x02a9), (kernel_ulong_t)&spt_uart_info },
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]