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/linux-6.14.4/arch/arm/mach-s3c/
Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dqcom,pcie-x1e80100.yaml93 reg = <0 0x01c08000 0 0x3000>,
94 <0 0x7c000000 0 0xf1d>,
95 <0 0x7c000f40 0 0xa8>,
96 <0 0x7c001000 0 0x1000>,
97 <0 0x7c100000 0 0x100000>,
98 <0 0x01c0b000 0 0x1000>;
100 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
101 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
103 bus-range = <0x00 0xff>;
105 linux,pci-domain = <0>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]