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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/linux-6.14.4/sound/soc/amd/acp/
Damd.h22 #define DMIC_INSTANCE 0x00
23 #define I2S_SP_INSTANCE 0x01
24 #define I2S_BT_INSTANCE 0x02
25 #define I2S_HS_INSTANCE 0x03
27 #define MEM_WINDOW_START 0x4080000
29 #define ACP_I2S_REG_START 0x1242400
30 #define ACP_I2S_REG_END 0x1242810
31 #define ACP3x_I2STDM_REG_START 0x1242400
32 #define ACP3x_I2STDM_REG_END 0x1242410
33 #define ACP3x_BT_TDM_REG_START 0x1242800
[all …]
/linux-6.14.4/arch/mips/boot/dts/ingenic/
Dci20.dts27 reg = <0x0 0x10000000
28 0x30000000 0x30000000>;
45 led-0 {
65 gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
70 eth0_power: fixedregulator-0 {
77 gpio = <&gpb 25 0>;
110 gpio = <&gpb 19 0>;
121 gpio = <&gpf 15 0>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsm8750.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0 0x0>;
46 reg = <0x0 0x100>;
56 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
76 reg = <0x0 0x400>;
86 reg = <0x0 0x500>;
96 reg = <0x0 0x10000>;
112 reg = <0x0 0x10100>;
[all …]
Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]