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/linux-6.14.4/drivers/video/fbdev/
Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt8192.c27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
36 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
[all …]
Dclk-mt8183.c35 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
36 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
37 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
44 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
[all …]
Dclk-mt6779.c640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_4_1_sdm670.h13 .base = 0x0, .len = 0x45c,
16 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
17 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
18 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
19 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
20 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
27 .base = 0x4000, .len = 0x1c8,
30 .xin_id = 0,
35 .base = 0x6000, .len = 0x1c8,
43 .base = 0x24000, .len = 0x1c8,
[all …]
Ddpu_6_0_sm8250.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_7_0_sm8350.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_5_0_sm8150.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_5_1_sc8180x.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x290,
39 .base = 0x16000, .len = 0x290,
44 .base = 0x17000, .len = 0x290,
49 .base = 0x18000, .len = 0x290,
54 .base = 0x19000, .len = 0x290,
59 .base = 0x1a000, .len = 0x290,
68 .base = 0x4000, .len = 0x344,
[all …]
Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
33 .base = 0x15000, .len = 0x290,
38 .base = 0x16000, .len = 0x290,
43 .base = 0x17000, .len = 0x290,
48 .base = 0x18000, .len = 0x290,
53 .base = 0x19000, .len = 0x290,
58 .base = 0x1a000, .len = 0x290,
67 .base = 0x4000, .len = 0x344,
[all …]
Ddpu_3_2_sdm660.h11 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
39 .base = 0x1000, .len = 0x94,
44 .base = 0x1200, .len = 0x94,
[all …]
Ddpu_1_7_msm8996.h13 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x454,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
32 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
33 [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 },
34 [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 },
[all …]
Ddpu_4_0_sdm845.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_3_0_msm8998.h12 .max_mixer_blendstages = 0x7,
25 .base = 0x0, .len = 0x458,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
[all …]
Ddpu_5_2_sm7150.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
40 .base = 0x1000, .len = 0x1e0,
45 .base = 0x1200, .len = 0x1e0,
[all …]
Ddpu_5_3_sm6150.h11 .max_mixer_blendstages = 0x9,
22 .base = 0x0, .len = 0x45c,
23 .features = 0,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
36 .base = 0x1000, .len = 0x1e0,
41 .base = 0x1200, .len = 0x1e0,
[all …]
Ddpu_7_2_sc7280.h12 .max_mixer_blendstages = 0x7,
21 .base = 0x0, .len = 0x2014,
23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 .base = 0x15000, .len = 0x1e8,
39 .base = 0x16000, .len = 0x1e8,
44 .base = 0x17000, .len = 0x1e8,
[all …]
Ddpu_1_14_msm8937.h11 .max_mixer_blendstages = 0x4,
21 .base = 0x0, .len = 0x454,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
26 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
28 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
36 .base = 0x1000, .len = 0x64,
39 .base = 0x1200, .len = 0x64,
42 .base = 0x1400, .len = 0x64,
[all …]
Ddpu_3_3_sdm630.h11 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
31 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
38 .base = 0x1000, .len = 0x94,
43 .base = 0x1200, .len = 0x94,
47 .base = 0x1400, .len = 0x94,
[all …]
Ddpu_6_2_sc7180.h12 .max_mixer_blendstages = 0x9,
21 .base = 0x0, .len = 0x494,
23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 .base = 0x1000, .len = 0x1dc,
39 .base = 0x1200, .len = 0x1dc,
44 .base = 0x1400, .len = 0x1dc,
[all …]
/linux-6.14.4/include/dt-bindings/clock/
Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux-6.14.4/arch/sh/include/mach-common/mach/
Dlboxre2.h12 #define IRQ_CF1 evt2irq(0x320) /* CF1 */
13 #define IRQ_CF0 evt2irq(0x340) /* CF0 */
14 #define IRQ_INTD evt2irq(0x360) /* INTD */
15 #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
16 #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
17 #define IRQ_INTA evt2irq(0x3c0) /* INTA */

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