/linux-6.14.4/Documentation/devicetree/bindings/reset/ |
D | qcom,aoss-reset.yaml | 50 reg = <0xc2a0000 0x31000>;
|
/linux-6.14.4/arch/arm/boot/dts/unisoc/ |
D | rda8810pl.dtsi | 19 #size-cells = <0>; 21 cpu@0 { 24 reg = <0x0>; 30 reg = <0x100000 0x10000>; 40 ranges = <0x0 0x10000000 0xfffffff>; 44 reg = <0x1a08000 0x1000>; 55 ranges = <0x0 0x20800000 0x100000>; 57 intc: interrupt-controller@0 { 59 reg = <0x0 0x1000>; 69 ranges = <0x0 0x20900000 0x100000>; [all …]
|
/linux-6.14.4/arch/arm/boot/dts/broadcom/ |
D | bcm-hr2.dtsi | 45 #size-cells = <0>; 47 cpu0: cpu@0 { 51 reg = <0x0>; 64 ranges = <0x00000000 0x19000000 0x00023000>; 68 a9pll: arm_clk@0 { 69 #clock-cells = <0>; 72 reg = <0x0 0x1000>; 77 reg = <0x20200 0x100>; 84 reg = <0x20600 0x20>; 92 reg = <0x20620 0x20>; [all …]
|
D | bcm-nsp.dtsi | 54 #size-cells = <0>; 56 cpu0: cpu@0 { 60 reg = <0x0>; 68 secondary-boot-reg = <0xffff0fec>; 69 reg = <0x1>; 82 ranges = <0x00000000 0x19000000 0x00023000>; 86 a9pll: arm_clk@0 { 87 #clock-cells = <0>; 90 reg = <0x00000 0x1000>; 95 reg = <0x20200 0x100>; [all …]
|
/linux-6.14.4/arch/arm/boot/dts/ti/omap/ |
D | omap2430.dtsi | 18 ranges = <0 0x49000000 0x31000>; 22 reg = <0x6000 0x1000>; 26 #size-cells = <0>; 35 reg = <0x2000 0x1000>; 39 ranges = <0 0x2000 0x1000>; 44 reg = <0x30 0x0154>; 46 #size-cells = <0>; 49 pinctrl-single,function-mask = <0x3f>; 55 reg = <0x270 0x240>; 58 ranges = <0 0x270 0x240>; [all …]
|
D | am33xx-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x44c00000 */ [all …]
|
D | am437x-l4.dtsi | 1 &l4_wkup { /* 0x44c00000 */ 4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 6 reg = <0x44c00000 0x800>, 7 <0x44c00800 0x800>, 8 <0x44c01000 0x400>, 9 <0x44c01400 0x400>; 13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x44c00000 */ [all …]
|
/linux-6.14.4/drivers/rapidio/switches/ |
D | idt_gen3.c | 18 #define RIO_EM_PW_STAT 0x40020 19 #define RIO_PW_CTL 0x40204 20 #define RIO_PW_CTL_PW_TMR 0xffffff00 21 #define RIO_PW_ROUTE 0x40208 23 #define RIO_EM_DEV_INT_EN 0x40030 25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100) 26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000 28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100) 29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000 30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000 [all …]
|
/linux-6.14.4/arch/powerpc/boot/dts/fsl/ |
D | t1023si-post.dtsi | 39 alloc-ranges = <0 0 0x10000 0>; 44 alloc-ranges = <0 0 0x10000 0>; 49 alloc-ranges = <0 0 0x10000 0>; 56 interrupts = <25 2 0 0>; 64 bus-range = <0x0 0xff>; 65 interrupts = <20 2 0 0>; 67 pcie@0 { 68 reg = <0 0 0 0 0>; 73 interrupts = <20 2 0 0>; 74 interrupt-map-mask = <0xf800 0 0 7>; [all …]
|
D | b4si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 71 reg = <0 0 0 0 0>; 72 interrupts = <20 2 0 0>; [all …]
|
D | t2081si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 67 reg = <0 0 0 0 0>; [all …]
|
D | t1040si-post.dtsi | 39 alloc-ranges = <0 0 0x10000 0>; 44 alloc-ranges = <0 0 0x10000 0>; 49 alloc-ranges = <0 0 0x10000 0>; 56 interrupts = <25 2 0 0>; 64 bus-range = <0x0 0xff>; 65 interrupts = <20 2 0 0>; 67 pcie@0 { 68 reg = <0 0 0 0 0>; 73 interrupts = <20 2 0 0>; 74 interrupt-map-mask = <0xf800 0 0 7>; [all …]
|
D | t4240si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 65 pcie@0 { 70 reg = <0 0 0 0 0>; [all …]
|
/linux-6.14.4/drivers/net/ethernet/meta/fbnic/ |
D | fbnic_csr.h | 16 #define MIN_FW_MAJOR_VERSION 0 23 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013 29 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0) 33 FBNIC_TWD_L3_TYPE_OTHER = 0, 43 FBNIC_TWD_L4_TYPE_OTHER = 0, 62 FBNIC_TWD_TYPE_META = 0, 71 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0) 72 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0) 76 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0) 79 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0) [all …]
|
/linux-6.14.4/arch/arm64/boot/dts/qcom/ |
D | sc7180.dtsi | 66 #clock-cells = <0>; 72 #clock-cells = <0>; 78 #size-cells = <0>; 80 cpu0: cpu@0 { 83 reg = <0x0 0x0>; 84 clocks = <&cpufreq_hw 0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 112 reg = <0x0 0x100>; 113 clocks = <&cpufreq_hw 0>; 124 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
D | sm6350.dtsi | 32 #clock-cells = <0>; 40 #clock-cells = <0>; 46 #size-cells = <0>; 48 cpu0: cpu@0 { 51 reg = <0x0 0x0>; 52 clocks = <&cpufreq_hw 0>; 57 qcom,freq-domain = <&cpufreq_hw 0>; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
D | sdm845.dtsi | 78 #clock-cells = <0>; 85 #clock-cells = <0>; 92 #size-cells = <0>; 94 cpu0: cpu@0 { 97 reg = <0x0 0x0>; 98 clocks = <&cpufreq_hw 0>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 126 reg = <0x0 0x100>; 127 clocks = <&cpufreq_hw 0>; 131 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
/linux-6.14.4/drivers/clk/qcom/ |
D | gcc-ipq5424.c | 55 .offset = 0x20000, 58 .enable_reg = 0xb000, 59 .enable_mask = BIT(0), 83 .offset = 0x21000, 86 .enable_reg = 0xb000, 98 { 0x1, 2 }, 103 .offset = 0x21000, 118 .offset = 0x22000, 121 .enable_reg = 0xb000, 144 { P_XO, 0 }, [all …]
|
D | gcc-msm8916.c | 45 .l_reg = 0x21004, 46 .m_reg = 0x21008, 47 .n_reg = 0x2100c, 48 .config_reg = 0x21010, 49 .mode_reg = 0x21000, 50 .status_reg = 0x2101c, 63 .enable_reg = 0x45000, 64 .enable_mask = BIT(0), 76 .l_reg = 0x20004, 77 .m_reg = 0x20008, [all …]
|
D | gcc-msm8996.c | 49 .offset = 0x00000, 52 .enable_reg = 0x52000, 53 .enable_mask = BIT(0), 79 .offset = 0x00000, 94 .enable_reg = 0x5200c, 95 .enable_mask = BIT(0), 111 .enable_reg = 0x5200c, 126 .offset = 0x77000, 129 .enable_reg = 0x52000, 143 .offset = 0x77000, [all …]
|
D | gcc-ipq5332.c | 53 .offset = 0x20000, 56 .enable_reg = 0xb000, 57 .enable_mask = BIT(0), 80 .offset = 0x20000, 93 .offset = 0x21000, 96 .enable_reg = 0xb000, 108 .offset = 0x21000, 121 .offset = 0x22000, 124 .enable_reg = 0xb000, 136 .offset = 0x22000, [all …]
|
D | gcc-ipq9574.c | 58 { P_XO, 0 }, 70 .offset = 0x20000, 73 .enable_reg = 0x0b000, 74 .enable_mask = BIT(0), 98 .offset = 0x20000, 112 .offset = 0x22000, 115 .enable_reg = 0x0b000, 127 .offset = 0x22000, 141 .offset = 0x21000, 144 .enable_reg = 0x0b000, [all …]
|
D | gcc-msm8939.c | 53 .l_reg = 0x21004, 54 .m_reg = 0x21008, 55 .n_reg = 0x2100c, 56 .config_reg = 0x21010, 57 .mode_reg = 0x21000, 58 .status_reg = 0x2101c, 71 .enable_reg = 0x45000, 72 .enable_mask = BIT(0), 84 .l_reg = 0x20004, 85 .m_reg = 0x20008, [all …]
|
D | gcc-x1e80100.c | 52 .offset = 0x0, 55 .enable_reg = 0x52030, 56 .enable_mask = BIT(0), 69 { 0x1, 2 }, 74 .offset = 0x0, 91 .offset = 0x4000, 94 .enable_reg = 0x52030, 108 .offset = 0x7000, 111 .enable_reg = 0x52030, 125 .offset = 0x8000, [all …]
|
/linux-6.14.4/drivers/net/ethernet/broadcom/bnx2x/ |
D | bnx2x_dump.h | 22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80 23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80 24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80 25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80 45 #define BNX2X_DUMP_VERSION 0x61111111 65 static const u32 page_vals_e2[] = {0, 128}; 68 {0x58000, 4608, DUMP_CHIP_E2, 0x30} 74 static const u32 page_vals_e3[] = {0, 128}; 77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30} 81 { 0x2000, 1, 0x1f, 0xfff}, [all …]
|