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/linux-6.14.4/Documentation/devicetree/bindings/interconnect/
Dqcom,sc7280-rpmh.yaml111 reg = <0x9100000 0xe2200>;
118 reg = <0x016e0000 0x1c080>;
/linux-6.14.4/drivers/interconnect/qcom/
Dsar2130p.c239 .port_offsets = { 0x9e000 },
241 .urg_fwd = 0,
257 .port_offsets = { 0x9f000 },
259 .urg_fwd = 0,
285 .port_offsets = { 0xe000, 0x4e000 },
286 .prio = 0,
287 .urg_fwd = 0,
303 .port_offsets = { 0xf000, 0x4f000 },
304 .prio = 0,
320 .port_offsets = { 0x9d000 },
[all …]
Dsc7280.c27 .port_offsets = { 0x7000 },
29 .urg_fwd = 0,
42 .port_offsets = { 0x11000 },
44 .urg_fwd = 0,
57 .port_offsets = { 0x8000 },
59 .urg_fwd = 0,
81 .port_offsets = { 0xc000 },
83 .urg_fwd = 0,
96 .port_offsets = { 0xe000 },
98 .urg_fwd = 0,
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]