Searched +full:0 +full:x18300000 (Results 1 – 5 of 5) sorted by relevance
59 minimum: 082 reg = <0x18300000 0x100000>;83 interrupts = <0 170 0>;96 qcom,ee = <0>;
34 reg = <0x60000000 0x10000000>;65 flash@0 {67 reg = <0x0 0x04000000>;68 pinctrl-0 = <&flash_pins>;77 partition@0 {79 reg = <0x00000000 0x00040000>;84 reg = <0x00040000 0x00040000>;89 reg = <0x00080000 0x03f80000>;96 reg = <0x18300000 0x1000>;99 interrupts-extended = <&irqpin 0 IRQ_TYPE_EDGE_FALLING>;[all …]
17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */26 #define AR5312_MISC_IRQ_TIMER 041 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet44 #define AR5312_WLAN0_BASE 0x1800000045 #define AR5312_ENET0_BASE 0x1810000046 #define AR5312_ENET1_BASE 0x18200000[all …]
26 #clock-cells = <0>;31 #clock-cells = <0>;37 #clock-cells = <0>;42 #clock-cells = <0>;48 #size-cells = <0>;50 cpu0: cpu@0 {53 reg = <0x0>;66 reg = <0x1>;79 reg = <0x2>;92 reg = <0x3>;[all …]
23 #size-cells = <0>;25 cpu0: cpu@0 {29 reg = <0>;54 polling-delay-passive = <0>;55 polling-delay = <0>;56 thermal-sensors = <&tsens 0>;74 polling-delay-passive = <0>;75 polling-delay = <0>;94 polling-delay-passive = <0>;95 polling-delay = <0>;[all …]