Home
last modified time | relevance | path

Searched +full:0 +full:x12c (Results 1 – 25 of 242) sorted by relevance

12345678910

/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c17 * So we model these clocks' rate as 0, to denote it's not an actual rate.
19 #define DUMMY_RATE 0
23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
24 _gate, 0, -1, _flags)
362 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
363 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
364 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
365 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
370 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
371 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
[all …]
Dclk-mt8173-topckgen.c18 * So we model these clocks' rate as 0, to denote it's not an actual rate.
20 #define DUMMY_RATE 0
24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
25 _gate, 0, -1, _flags)
437 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
438 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
439 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
440 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
445 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
446 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
[all …]
/linux-6.14.4/drivers/clk/visconti/
Dclkc-tmpv770x.c35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
[all …]
/linux-6.14.4/drivers/media/pci/cx18/
Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/linux-6.14.4/drivers/clk/sunxi-ng/
Dccu-sun50i-h6-r.c29 { .index = 3, .shift = 0, .width = 5 },
44 .reg = 0x000,
49 0),
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
69 .reg = 0x010,
74 0),
86 0x11c, BIT(0), 0);
88 0x12c, BIT(0), 0);
90 0x13c, BIT(0), 0);
[all …]
Dccu-sun20i-d1-r.c26 r_ahb_apb0_parents, 0x000,
27 0, 5, /* M */
30 0);
34 r_ahb_apb0_parents, 0x00c,
35 0, 5, /* M */
38 0);
42 0x11c, BIT(0), 0);
44 0x12c, BIT(0), 0);
46 0x1ac, BIT(0), 0);
53 r_ir_rx_parents, 0x1c0,
[all …]
/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-pcs-ufs-v6.h10 #define QPHY_V6_PCS_UFS_PHY_START 0x000
11 #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V6_PCS_UFS_SW_RESET 0x008
13 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
14 #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
15 #define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020
16 #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
17 #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
18 #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
19 #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
[all …]
Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_EN_CENTER 0x010
12 #define QSERDES_PLL_SSC_ADJ_PER1 0x014
13 #define QSERDES_PLL_SSC_ADJ_PER2 0x018
14 #define QSERDES_PLL_SSC_PER1 0x01c
15 #define QSERDES_PLL_SSC_PER2 0x020
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
18 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
19 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
/linux-6.14.4/drivers/soc/tegra/fuse/
Dfuse-tegra30.c21 #define FUSE_BEGIN 0x100
24 #define FUSE_VENDOR_CODE 0x100
25 #define FUSE_FAB_CODE 0x104
26 #define FUSE_LOT_CODE_0 0x108
27 #define FUSE_LOT_CODE_1 0x10c
28 #define FUSE_WAFER_ID 0x110
29 #define FUSE_X_COORDINATE 0x114
30 #define FUSE_Y_COORDINATE 0x118
32 #define FUSE_HAS_REVISION_INFO BIT(0)
46 return 0; in tegra30_fuse_read_early()
[all …]
Dspeedo-tegra114.c25 {0, UINT_MAX},
30 {0, UINT_MAX},
41 case 0x00: in rev_sku_to_speedo_ids()
42 case 0x10: in rev_sku_to_speedo_ids()
43 case 0x05: in rev_sku_to_speedo_ids()
44 case 0x06: in rev_sku_to_speedo_ids()
46 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids()
50 case 0x03: in rev_sku_to_speedo_ids()
51 case 0x04: in rev_sku_to_speedo_ids()
59 sku_info->cpu_speedo_id = 0; in rev_sku_to_speedo_ids()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dqcom,ipq5332-usb-hsphy.yaml25 const: 0
51 reg = <0x0007b000 0x12c>;
56 #phy-cells = <0>;
/linux-6.14.4/drivers/video/fbdev/
Dwm8505fb_regs.h15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
/linux-6.14.4/arch/arm/mach-davinci/
Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/vf/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/linux-6.14.4/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-lpc18xx.c23 #define LPC18XX_CREG_CREG6 0x12c
24 # define LPC18XX_CREG_CREG6_ETHMODE_MASK 0x7
25 # define LPC18XX_CREG_CREG6_ETHMODE_MII 0x0
26 # define LPC18XX_CREG_CREG6_ETHMODE_RMII 0x4
/linux-6.14.4/include/linux/mfd/
Didt82p33_reg.h10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
[all …]
/linux-6.14.4/sound/soc/tegra/
Dtegra210_mvc.h16 #define TEGRA210_MVC_RX_STATUS 0x0c
17 #define TEGRA210_MVC_RX_INT_STATUS 0x10
18 #define TEGRA210_MVC_RX_INT_MASK 0x14
19 #define TEGRA210_MVC_RX_INT_SET 0x18
20 #define TEGRA210_MVC_RX_INT_CLEAR 0x1c
21 #define TEGRA210_MVC_RX_CIF_CTRL 0x20
27 #define TEGRA210_MVC_TX_STATUS 0x4c
28 #define TEGRA210_MVC_TX_INT_STATUS 0x50
29 #define TEGRA210_MVC_TX_INT_MASK 0x54
30 #define TEGRA210_MVC_TX_INT_SET 0x58
[all …]
/linux-6.14.4/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dinput_formatter_local.h18 #define HIVE_IF_FSM_SYNC_STATUS 0x100
19 #define HIVE_IF_FSM_SYNC_COUNTER 0x104
20 #define HIVE_IF_FSM_DEINTERLEAVING_IDX 0x114
21 #define HIVE_IF_FSM_DECIMATION_H_COUNTER 0x118
22 #define HIVE_IF_FSM_DECIMATION_V_COUNTER 0x11C
23 #define HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER 0x120
24 #define HIVE_IF_FSM_PADDING_STATUS 0x124
25 #define HIVE_IF_FSM_PADDING_ELEMENT_COUNTER 0x128
26 #define HIVE_IF_FSM_VECTOR_SUPPORT_ERROR 0x12C
27 #define HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL 0x130
[all …]

12345678910