Searched +full:0 +full:x1294 (Results 1 – 25 of 32) sorted by relevance
12
88 reg = <0x12800000 0x1294>;
153 cluster_a15_opp_table: opp-table-0 {270 reg = <0x10d20000 0x1000>;271 ranges = <0x0 0x10d20000 0x6000>;276 reg = <0x4000 0x1000>;281 reg = <0x5000 0x1000>;287 reg = <0x10010000 0x30000>;293 reg = <0x03810000 0x0c>;303 reg = <0x11000000 0x10000>;316 #size-cells = <0>;317 reg = <0x12200000 0x2000>;[all …]
10 #define RCC_SECCFGR0 0x011 #define RCC_SECCFGR1 0x412 #define RCC_SECCFGR2 0x813 #define RCC_SECCFGR3 0xC14 #define RCC_PRIVCFGR0 0x1015 #define RCC_PRIVCFGR1 0x1416 #define RCC_PRIVCFGR2 0x1817 #define RCC_PRIVCFGR3 0x1C18 #define RCC_RCFGLOCKR0 0x2019 #define RCC_RCFGLOCKR1 0x24[all …]
48 #clock-cells = <0>;53 #size-cells = <0>;91 reg = <0x100>;96 i-cache-size = <0x8000>;99 d-cache-size = <0x8000>;109 reg = <0x101>;112 i-cache-size = <0x8000>;115 d-cache-size = <0x8000>;125 reg = <0x102>;128 i-cache-size = <0x8000>;[all …]
17 #define USB_VENDOR_ID_258A 0x258a18 #define USB_DEVICE_ID_258A_6A88 0x6a8820 #define USB_VENDOR_ID_3M 0x059621 #define USB_DEVICE_ID_3M1968 0x050022 #define USB_DEVICE_ID_3M2256 0x050223 #define USB_DEVICE_ID_3M3266 0x050625 #define USB_VENDOR_ID_A4TECH 0x09da26 #define USB_DEVICE_ID_A4TECH_WCP32PU 0x000627 #define USB_DEVICE_ID_A4TECH_X5_005D 0x000a28 #define USB_DEVICE_ID_A4TECH_RP_649 0x001a[all …]
18 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \24 for (; i-- > 0; ) \45 #define RSWITCH_TOP_OFFSET 0x0000800046 #define RSWITCH_COMA_OFFSET 0x0000900047 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */48 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */49 #define RSWITCH_GWCA0_OFFSET 0x0001000050 #define RSWITCH_GWCA1_OFFSET 0x0001200056 #define GWCA_INDEX 058 #define GWCA_IPV_NUM 0[all …]
23 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");33 } while (0)56 { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 }, in dib3000mc_read_word()64 return 0; in dib3000mc_read_word()66 b[0] = (reg >> 8) | 0x80; in dib3000mc_read_word()68 b[2] = 0; in dib3000mc_read_word()69 b[3] = 0; in dib3000mc_read_word()71 msg[0].buf = b; in dib3000mc_read_word()86 .addr = state->i2c_addr >> 1, .flags = 0, .len = 4 in dib3000mc_write_word()[all …]
16 #define ID_REV (0x00)17 #define ID_REV_ID_MASK_ (0xFFFF0000)18 #define ID_REV_ID_LAN7430_ (0x74300000)19 #define ID_REV_ID_LAN7431_ (0x74310000)20 #define ID_REV_ID_LAN743X_ (0x74300000)21 #define ID_REV_ID_A011_ (0xA0110000) // PCI1101022 #define ID_REV_ID_A041_ (0xA0410000) // PCI1141423 #define ID_REV_ID_A0X1_ (0xA0010000)25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))[all …]
31 // base address: 0x032 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x000033 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x000134 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x000235 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x000336 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x000437 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x000538 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x000639 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x000740 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008[all …]
27 // base address: 0x028 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293430 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293535 // base address: 0x36036 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d43 // base address: 0x6c044 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae446 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae551 // base address: 0xa20[all …]
14 // base address: 0x015 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293417 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293522 // base address: 0x36023 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d30 // base address: 0x6c031 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae433 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae538 // base address: 0xa20[all …]
31 // base address: 0x032 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293434 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293539 // base address: 0x36040 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d47 // base address: 0x6c048 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae450 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae555 // base address: 0xa20[all …]
13 #define AFE_SRAM_BASE (0x10880000)14 #define AFE_SRAM_SIZE (0x10000)16 #define AUDIO_TOP_CON0 (0x0000)17 #define AUDIO_TOP_CON1 (0x0004)18 #define AUDIO_TOP_CON2 (0x0008)19 #define AUDIO_TOP_CON3 (0x000c)20 #define AUDIO_TOP_CON4 (0x0010)21 #define AUDIO_TOP_CON5 (0x0014)22 #define AUDIO_TOP_CON6 (0x0018)23 #define AFE_MAS_HADDR_MSB (0x0020)[all …]
14 #define AUDIO_TOP_CON0 (0x0000)15 #define AUDIO_TOP_CON1 (0x0004)16 #define AUDIO_TOP_CON2 (0x0008)17 #define AUDIO_TOP_CON3 (0x000c)18 #define AUDIO_TOP_CON4 (0x0010)19 #define AUDIO_TOP_CON5 (0x0014)20 #define AUDIO_TOP_CON6 (0x0018)21 #define AFE_MAS_HADDR_MSB (0x0020)22 #define AFE_MEMIF_ONE_HEART (0x0024)23 #define AFE_MUX_SEL_CFG (0x0044)[all …]
27 // base address: 0x028 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x004030 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x004132 …DP_DTO_DBUF_EN 0x004434 …DPREFCLK_CGTT_BLK_CTRL_REG 0x004836 …REFCLK_CNTL 0x004938 …REFCLK_CGTT_BLK_CTRL_REG 0x004b40 …DCCG_PERFMON_CNTL2 0x004e42 …DCCG_DS_DTO_INCR 0x005344 …DCCG_DS_DTO_MODULO 0x0054[all …]
29 // base address: 0x030 …DIDT_SQ_CTRL0 0x000031 …DIDT_SQ_CTRL2 0x000232 …DIDT_SQ_STALL_CTRL 0x000433 …DIDT_SQ_TUNING_CTRL 0x000534 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x000635 …DIDT_SQ_CTRL3 0x000736 …DIDT_SQ_STALL_PATTERN_1_2 0x000837 …DIDT_SQ_STALL_PATTERN_3_4 0x000938 …DIDT_SQ_STALL_PATTERN_5_6 0x000a[all …]
24 …SQ_DEBUG_STS_GLOBAL 0x030925 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 026 …SQ_DEBUG_STS_GLOBAL2 0x031027 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 028 …SQ_DEBUG_STS_GLOBAL3 0x031129 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 032 // base address: 0x800033 …GRBM_CNTL 0x000034 …ne mmGRBM_CNTL_BASE_IDX 035 …GRBM_SKEW_CNTL 0x0001[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_F32_MISC_CNTL 0x000b33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 034 …SDMA0_UCODE_VERSION 0x000d35 …e regSDMA0_UCODE_VERSION_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 038 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010[all …]
24 …SQ_DEBUG_STS_GLOBAL 0x10A925 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 026 …SQ_DEBUG_STS_GLOBAL2 0x10B027 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 030 // base address: 0x498031 …SDMA0_DEC_START 0x000032 …ne mmSDMA0_DEC_START_BASE_IDX 033 …SDMA0_PG_CNTL 0x001634 …ne mmSDMA0_PG_CNTL_BASE_IDX 035 …SDMA0_PG_CTX_LO 0x0017[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_F32_MISC_CNTL 0x000b33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 034 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_HI 0x001037 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 038 …SDMA0_POWER_CNTL 0x001a[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_MCU_MISC_CNTL 0x000133 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 034 …SDMA0_UCODE_REV 0x000335 …e regSDMA0_UCODE_REV_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000537 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 038 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006[all …]
51 #define OPTION_VENDOR_ID 0x0AF052 #define OPTION_PRODUCT_COLT 0x500053 #define OPTION_PRODUCT_RICOLA 0x600054 #define OPTION_PRODUCT_RICOLA_LIGHT 0x610055 #define OPTION_PRODUCT_RICOLA_QUAD 0x620056 #define OPTION_PRODUCT_RICOLA_QUAD_LIGHT 0x630057 #define OPTION_PRODUCT_RICOLA_NDIS 0x605058 #define OPTION_PRODUCT_RICOLA_NDIS_LIGHT 0x615059 #define OPTION_PRODUCT_RICOLA_NDIS_QUAD 0x625060 #define OPTION_PRODUCT_RICOLA_NDIS_QUAD_LIGHT 0x6350[all …]