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Searched +full:0 +full:x11c10000 (Results 1 – 16 of 16) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dmediatek,mt8365-csi-rx.yaml32 enum: [0, 1]
34 If the PHY doesn't support mode selection then #phy-cells must be 0 and
66 reg = <0 0x11c10000 0 0x2000>;
73 reg = <0 0x11c12000 0 0x2000>;
76 #phy-cells = <0>;
/linux-6.14.4/Documentation/devicetree/bindings/nvmem/
Dmediatek,efuse.yaml23 pattern: "^efuse@[0-9a-f]+$"
58 reg = <0x11c10000 0x1000>;
63 reg = <0x184 0x1>;
64 bits = <0 5>;
67 reg = <0x184 0x2>;
71 reg = <0x185 0x1>;
75 reg = <0x186 0x1>;
76 bits = <0 5>;
79 reg = <0x186 0x2>;
83 reg = <0x187 0x1>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt7981b.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0x0>;
26 reg = <0x1>;
36 #clock-cells = <0>;
52 reg = <0 0x0c000000 0 0x40000>, /* GICD */
53 <0 0x0c080000 0 0x200000>; /* GICR */
62 reg = <0 0x10001000 0 0x1000>;
68 reg = <0 0x1001b000 0 0x1000>;
74 reg = <0 0x1001c000 0 0x1000>;
[all …]
Dmt7988a.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
21 reg = <0x0>;
32 reg = <0x1>;
43 reg = <0x2>;
54 reg = <0x3>;
63 cluster0_opp: opp-table-0 {
89 #clock-cells = <0>;
111 reg = <0 0x43000000 0 0x50000>;
124 reg = <0 0x0c000000 0 0x40000>, /* GICD */
[all …]
Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dmediatek,mt7981-pinctrl.yaml85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
396 enum: [0, 1, 2, 3]
400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
[all …]
Dmediatek,mt7988-pinctrl.yaml81 "tops_jtag0_0" "jtag" 0, 1, 2, 3, 4
102 "dfd" "dfd" 0, 1, 2, 3, 4
103 "xfi_phy0_i2c0" "i2c" 0, 1
104 "xfi_phy1_i2c0" "i2c" 0, 1
163 "uart2" "uart" 0, 1, 2, 3
446 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
449 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
450 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
451 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
454 enum: [0, 1, 2, 3]
[all …]
/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr9a08g045.dtsi19 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
37 reg = <0>;
45 L3_CA55: cache-controller-0 {
49 cache-size = <0x40000>;
55 #clock-cells = <0>;
[all …]
Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/tesla/
Dfsd.dtsi39 #size-cells = <0>;
88 /* Cluster 0 */
89 cpucl0_0: cpu@0 {
92 reg = <0x0 0x000>;
96 i-cache-size = <0xc000>;
99 d-cache-size = <0x8000>;
108 reg = <0x0 0x001>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
124 reg = <0x0 0x002>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/samsung/
Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/linux-6.14.4/drivers/clk/samsung/
Dclk-fsd.c23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0
25 #define PLL_LOCKTIME_PLL_SHARED1 0x4
26 #define PLL_LOCKTIME_PLL_SHARED2 0x8
27 #define PLL_LOCKTIME_PLL_SHARED3 0xc
28 #define PLL_CON0_PLL_SHARED0 0x100
29 #define PLL_CON0_PLL_SHARED1 0x120
30 #define PLL_CON0_PLL_SHARED2 0x140
31 #define PLL_CON0_PLL_SHARED3 0x160
32 #define MUX_CMU_CIS0_CLKMUX 0x1000
[all …]