Searched +full:0 +full:x11830000 (Results 1 – 7 of 7) sorted by relevance
67 bits[0:9] - Specifies MID/RID value125 reg = <0x11820000 0x10000>,126 <0x11830000 0x10000>;
35 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0x0>;73 reg = <0x1>;80 reg = <0x100>;87 reg = <0x101>;94 reg = <0x102>;101 reg = <0x103>;114 reg = <0x10010000 0x10000>;128 reg = <0x10200000 0x10000>;[all …]
199 #size-cells = <0>;212 cpu0: cpu@0 {215 reg = <0>;259 xusbxti: clock-0 {261 clock-frequency = <0>;262 #clock-cells = <0>;268 clock-frequency = <0>;269 #clock-cells = <0>;275 clock-frequency = <0>;276 #clock-cells = <0>;[all …]
19 #clock-cells = <0>;21 clock-frequency = <0>;26 #clock-cells = <0>;28 clock-frequency = <0>;33 #size-cells = <0>;35 cpu0: cpu@0 {37 reg = <0>;45 L3_CA55: cache-controller-0 {49 cache-size = <0x40000>;55 #clock-cells = <0>;[all …]
17 #clock-cells = <0>;19 clock-frequency = <0>;24 #clock-cells = <0>;26 clock-frequency = <0>;32 #clock-cells = <0>;33 clock-frequency = <0>;39 #clock-cells = <0>;41 clock-frequency = <0>;44 cluster0_opp: opp-table-0 {80 reg = <0 0x10001200 0 0xb00>;[all …]
18 #clock-cells = <0>;20 clock-frequency = <0>;25 #clock-cells = <0>;27 clock-frequency = <0>;33 #clock-cells = <0>;34 clock-frequency = <0>;40 #clock-cells = <0>;42 clock-frequency = <0>;45 cluster0_opp: opp-table-0 {74 #size-cells = <0>;[all …]