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/linux-6.14.4/arch/mips/boot/dts/xilfpga/
Dnexys4ddr.dts19 reg = <0x0 0x08000000>;
23 #address-cells = <0>;
33 reg = <0x10200000 0x10000>;
34 xlnx,kind-of-intr = <0x0>;
35 xlnx,num-intr-inputs = <0x6>;
45 reg = <0x10600000 0x10000>;
46 xlnx,all-inputs = <0x0>;
47 xlnx,dout-default = <0x0>;
48 xlnx,gpio-width = <0x16>;
49 xlnx,interrupt-present = <0x0>;
[all …]
/linux-6.14.4/include/linux/platform_data/
Dsh_mmcif.h31 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
36 #define MMCIF_CE_CMD_SET 0x00000000
37 #define MMCIF_CE_ARG 0x00000008
38 #define MMCIF_CE_ARG_CMD12 0x0000000C
39 #define MMCIF_CE_CMD_CTRL 0x00000010
40 #define MMCIF_CE_BLOCK_SET 0x00000014
41 #define MMCIF_CE_CLK_CTRL 0x00000018
42 #define MMCIF_CE_BUF_ACC 0x0000001C
43 #define MMCIF_CE_RESP3 0x00000020
44 #define MMCIF_CE_RESP2 0x00000024
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Drenesas,rzv2h-icu.yaml27 PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to
32 const: 0
153 - const: int-ca55-0
193 reg = <0x10400000 0x10000>;
195 #address-cells = <0>;
197 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
270 "int-ca55-0", "int-ca55-1",
275 clocks = <&cpg CPG_MOD 0x5>;
277 resets = <&cpg 0x36>;
/linux-6.14.4/arch/arm64/boot/dts/exynos/
Dexynosautov920.dtsi38 #clock-cells = <0>;
44 #size-cells = <0>;
87 cpu0: cpu@0 {
90 reg = <0x0 0x0>;
97 reg = <0x0 0x100>;
104 reg = <0x0 0x200>;
111 reg = <0x0 0x300>;
118 reg = <0x0 0x10000>;
125 reg = <0x0 0x10100>;
132 reg = <0x0 0x10200>;
[all …]
Dexynos8895.dtsi55 #size-cells = <0>;
89 cpu4: cpu@0 {
92 reg = <0x0>;
99 reg = <0x1>;
106 reg = <0x2>;
113 reg = <0x3>;
120 reg = <0x100>;
127 reg = <0x101>;
134 reg = <0x102>;
141 reg = <0x103>;
[all …]
/linux-6.14.4/arch/mips/ath25/
Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr9a09g057.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
58 #size-cells = <0>;
60 cpu0: cpu@0 {
62 reg = <0>;
72 reg = <0x100>;
82 reg = <0x200>;
92 reg = <0x300>;
100 L3_CA55: cache-controller-0 {
[all …]
/linux-6.14.4/arch/hexagon/kernel/
Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux-6.14.4/arch/arm64/boot/dts/tesla/
Dfsd.dtsi39 #size-cells = <0>;
88 /* Cluster 0 */
89 cpucl0_0: cpu@0 {
92 reg = <0x0 0x000>;
96 i-cache-size = <0xc000>;
99 d-cache-size = <0x8000>;
108 reg = <0x0 0x001>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
124 reg = <0x0 0x002>;
[all …]
/linux-6.14.4/arch/mips/include/asm/mach-au1x00/
Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/exynos/google/
Dgs101.dtsi34 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0000>;
84 reg = <0x0100>;
94 reg = <0x0200>;
104 reg = <0x0300>;
114 reg = <0x0400>;
124 reg = <0x0500>;
134 reg = <0x0600>;
144 reg = <0x0700>;
[all …]
/linux-6.14.4/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-6.14.4/drivers/clk/samsung/
Dclk-exynos8895.c29 /* Register Offset definitions for CMU_TOP (0x15a80000) */
30 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
31 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
32 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
33 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
34 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
35 #define PLL_CON0_MUX_CP2AP_MIF_CLK_USER 0x0100
36 #define PLL_CON2_MUX_CP2AP_MIF_CLK_USER 0x0108
37 #define PLL_CON0_PLL_SHARED0 0x0120
38 #define PLL_CON0_PLL_SHARED1 0x0140
[all …]
/linux-6.14.4/arch/parisc/kernel/
Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]