Searched +full:0 +full:x10011 (Results 1 – 4 of 4) sorted by relevance
/linux-6.14.4/Documentation/devicetree/bindings/perf/ |
D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff. 104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>; 105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, 106 <0x00002 0x00002 0x00000004>, 107 <0x00003 0x0000A 0x00000ff8>, 108 <0x10000 0x10033 0x000ff000>; 110 /* For event ID 0x0002 */ 111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>, 112 /* For event ID 0-4 */ 113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>, [all …]
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/linux-6.14.4/arch/riscv/boot/dts/thead/ |
D | th1520.dtsi | 17 #size-cells = <0>; 20 c910_0: cpu@0 { 27 reg = <0>; 129 <0x00003 0x00003 0x0007fff8>, 130 <0x00004 0x00004 0x0007fff8>, 131 <0x00005 0x00005 0x0007fff8>, 132 <0x00006 0x00006 0x0007fff8>, 133 <0x00007 0x00007 0x0007fff8>, 134 <0x00008 0x00008 0x0007fff8>, 135 <0x00009 0x00009 0x0007fff8>, [all …]
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/linux-6.14.4/drivers/perf/hisilicon/ |
D | hisi_pcie_pmu.c | 24 #define HISI_PCIE_GLOBAL_CTRL 0x00 25 #define HISI_PCIE_EVENT_CTRL 0x010 26 #define HISI_PCIE_CNT 0x090 27 #define HISI_PCIE_EXT_CNT 0x110 28 #define HISI_PCIE_INT_STAT 0x150 29 #define HISI_PCIE_INT_MASK 0x154 30 #define HISI_PCIE_REG_BDF 0xfe0 31 #define HISI_PCIE_REG_VERSION 0xfe4 32 #define HISI_PCIE_REG_INFO 0xfe8 35 #define HISI_PCIE_GLOBAL_EN 0x01 [all …]
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/linux-6.14.4/drivers/perf/ |
D | arm_v7_pmu.c | 37 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00 38 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01 39 #define ARMV7_PERFCTR_ITLB_REFILL 0x02 40 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03 41 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04 42 #define ARMV7_PERFCTR_DTLB_REFILL 0x05 43 #define ARMV7_PERFCTR_MEM_READ 0x06 44 #define ARMV7_PERFCTR_MEM_WRITE 0x07 45 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08 46 #define ARMV7_PERFCTR_EXC_TAKEN 0x09 [all …]
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