Home
last modified time | relevance | path

Searched +full:0 +full:x0c0 (Results 1 – 25 of 219) sorted by relevance

123456789

/linux-6.14.4/drivers/pinctrl/mediatek/
Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
Dpinctrl-mt8195.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
15 * iocfg[6]:0x11f40000.
21 32, 0)
28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
[all …]
Dpinctrl-mt6397.c17 #define MT6397_PIN_REG_BASE 0xc000
22 .dir_offset = (MT6397_PIN_REG_BASE + 0x000),
25 .pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
26 .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
27 .dout_offset = (MT6397_PIN_REG_BASE + 0x080),
28 .din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
29 .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
33 .port_mask = 0x3,
35 .mode_mask = 0xf,
/linux-6.14.4/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
[all …]
Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
76 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
77 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
78 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
[all …]
/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-dp-phy-v3.h10 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
11 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
12 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
14 #define QSERDES_V3_DP_PHY_VCO_DIV 0x064
15 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
16 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
18 #define QSERDES_V3_DP_PHY_SPARE0 0x0ac
19 #define QSERDES_V3_DP_PHY_STATUS 0x0c0
Dphy-qcom-qmp-pcs-v2.h10 #define QPHY_V2_PCS_SW_RESET 0x000
11 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_START_CONTROL 0x008
13 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
14 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
15 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
16 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
17 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
18 #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
19 #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
[all …]
/linux-6.14.4/sound/pci/oxygen/
Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/linux-6.14.4/drivers/nvmem/
Drcar-efuse.c25 unsigned int bank; /* 0: PFC + E-FUSE, 1: OPT_MEM + E-FUSE */
37 if (ret < 0) in rcar_fuse_reg_read()
44 return 0; in rcar_fuse_reg_read()
68 if (ret < 0) in rcar_fuse_probe()
81 fuse->keepouts[0].start = 0; in rcar_fuse_probe()
82 fuse->keepouts[0].end = data->start; in rcar_fuse_probe()
96 return 0; in rcar_fuse_probe()
100 .bank = 0,
101 .start = 0x0c0,
102 .end = 0x0e8,
[all …]
/linux-6.14.4/include/linux/spi/
Dmxs-spi.h19 #define HW_SSP_CTRL0 0x000
27 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
33 #define BP_SSP_CTRL0_XFER_COUNT 0
34 #define BM_SSP_CTRL0_XFER_COUNT 0xffff
35 #define HW_SSP_CMD0 0x010
41 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
43 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
44 #define BP_SSP_CMD0_CMD 0
45 #define BM_SSP_CMD0_CMD 0xff
46 #define HW_SSP_CMD1 0x020
[all …]
/linux-6.14.4/arch/sparc/lib/
Dbzero.S14 and %o1, 0xff, %o3
30 prefetch [%o0 + 0x000], #n_writes
31 andcc %o0, 0x3, %g0
33 1: stb %o2, [%o0 + 0x00]
35 andcc %o0, 0x3, %g0
38 2: andcc %o0, 0x7, %g0
40 stw %o2, [%o0 + 0x00]
43 3: and %o1, 0x38, %g1
44 cmp %o1, 0x40
45 andn %o1, 0x3f, %o4
[all …]
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt7988-topckgen.c107 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
108 0, 2, 7, 0x1c0, 0),
109 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
110 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
111 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
112 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
114 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
116 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
117 0x018, 0, 1, 7, 0x1C0, 4),
[all …]
/linux-6.14.4/drivers/net/wireless/broadcom/b43/
Dradio_2059.h9 #define R2059_C1 0x000
10 #define R2059_C2 0x400
11 #define R2059_C3 0x800
12 #define R2059_ALL 0xC00
14 #define R2059_RCAL_CONFIG 0x004
15 #define R2059_RFPLL_MASTER 0x011
16 #define R2059_RFPLL_MISC_EN 0x02b
17 #define R2059_RFPLL_MISC_CAL_RESETN 0x02e
18 #define R2059_XTAL_CONFIG2 0x0c0
19 #define R2059_RCCAL_START_R1_Q1_P1 0x13c
[all …]
Dtables_nphy.h74 #define B43_NTAB_TYPEMASK 0xF0000000
75 #define B43_NTAB_8BIT 0x10000000
76 #define B43_NTAB_16BIT 0x20000000
77 #define B43_NTAB_32BIT 0x30000000
83 #define B43_NTAB_FRAMESTRUCT B43_NTAB32(0x0A, 0x000) /* Frame Struct Table */
85 #define B43_NTAB_FRAMELT B43_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
87 #define B43_NTAB_TMAP B43_NTAB32(0x0C, 0x000) /* T Map Table */
89 #define B43_NTAB_TDTRN B43_NTAB32(0x0E, 0x000) /* TDTRN Table */
91 #define B43_NTAB_INTLEVEL B43_NTAB32(0x0D, 0x000) /* Int Level Table */
93 #define B43_NTAB_PILOT B43_NTAB16(0x0B, 0x000) /* Pilot Table */
[all …]
/linux-6.14.4/drivers/clk/meson/
Ds4-peripherals.h10 #define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008
11 #define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c
12 #define CLKCTRL_RTC_CTRL 0x010
13 #define CLKCTRL_SYS_CLK_CTRL0 0x040
14 #define CLKCTRL_SYS_CLK_EN0_REG0 0x044
15 #define CLKCTRL_SYS_CLK_EN0_REG1 0x048
16 #define CLKCTRL_SYS_CLK_EN0_REG2 0x04c
17 #define CLKCTRL_SYS_CLK_EN0_REG3 0x050
18 #define CLKCTRL_CECA_CTRL0 0x088
19 #define CLKCTRL_CECA_CTRL1 0x08c
[all …]
/linux-6.14.4/drivers/net/wireless/mediatek/mt76/mt7603/
Deeprom.h9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
16 MT_EE_XTAL_TRIM_1 = 0x03a,
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
[all …]
/linux-6.14.4/sound/soc/meson/
Daiu.h18 PCLK = 0,
62 #define AIU_IEC958_BPF 0x000
63 #define AIU_958_MISC 0x010
64 #define AIU_IEC958_DCU_FF_CTRL 0x01c
65 #define AIU_958_CHSTAT_L0 0x020
66 #define AIU_958_CHSTAT_L1 0x024
67 #define AIU_958_CTRL 0x028
68 #define AIU_I2S_SOURCE_DESC 0x034
69 #define AIU_I2S_DAC_CFG 0x040
70 #define AIU_I2S_SYNC 0x044
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/vf/
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/linux-6.14.4/drivers/staging/media/rkvdec/
Drkvdec-regs.h7 #define RKVDEC_REG_INTERRUPT 0x004
8 #define RKVDEC_INTERRUPT_DEC_E BIT(0)
32 #define RKVDEC_REG_SYSCTRL 0x008
33 #define RKVDEC_IN_ENDIAN BIT(0)
44 #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
45 #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
55 #define RKVDEC_REG_PICPAR 0x00C
56 #define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
58 #define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
59 #define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
[all …]
/linux-6.14.4/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_regs.h11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_MAX_LINE_SIZE 0x008
14 #define BLK_VALID_INPUT_ID0 0x020
15 #define BLK_OUTPUT_ID0 0x060
16 #define BLK_INPUT_ID0 0x080
17 #define BLK_IRQ_RAW_STATUS 0x0A0
18 #define BLK_IRQ_CLEAR 0x0A4
19 #define BLK_IRQ_MASK 0x0A8
20 #define BLK_IRQ_STATUS 0x0AC
[all …]

123456789