Searched +full:0 +full:x0bfc (Results 1 – 17 of 17) sorted by relevance
/linux-6.14.4/arch/arm/mach-imx/ |
D | iim.h | 11 #define MXC_IIMSTAT 0x0000 12 #define MXC_IIMSTATM 0x0004 13 #define MXC_IIMERR 0x0008 14 #define MXC_IIMEMASK 0x000C 15 #define MXC_IIMFCTL 0x0010 16 #define MXC_IIMUA 0x0014 17 #define MXC_IIMLA 0x0018 18 #define MXC_IIMSDAT 0x001C 19 #define MXC_IIMPREV 0x0020 20 #define MXC_IIMSREV 0x0024 [all …]
|
/linux-6.14.4/Documentation/devicetree/bindings/misc/ |
D | fsl,qoriq-mc.yaml | 58 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in 81 0x0 - MC portals 82 0x1 - QBMAN portals 140 const: 0 161 reg = <0x0c000000 0x40>, /* MC portal base */ 162 <0x08340000 0x40000>; /* MC control reg */ 164 * Region type 0x0 - MC portals 165 * Region type 0x1 - QBMAN portals 167 ranges = <0x0 0x0 0x8 0x0c000000 0x4000000 168 0x1 0x0 0x8 0x18000000 0x8000000>; [all …]
|
/linux-6.14.4/drivers/soc/fsl/qbman/ |
D | bman_ccsr.c | 37 #define REG_FBPR_FPC 0x0800 38 #define REG_ECSR 0x0a00 39 #define REG_ECIR 0x0a04 40 #define REG_EADR 0x0a08 41 #define REG_EDATA(n) (0x0a10 + ((n) * 0x04)) 42 #define REG_SBEC(n) (0x0a80 + ((n) * 0x04)) 43 #define REG_IP_REV_1 0x0bf8 44 #define REG_IP_REV_2 0x0bfc 45 #define REG_FBPR_BARE 0x0c00 46 #define REG_FBPR_BAR 0x0c04 [all …]
|
D | qman_ccsr.c | 41 #define REG_QCSP_LIO_CFG(n) (0x0000 + ((n) * 0x10)) 42 #define REG_QCSP_IO_CFG(n) (0x0004 + ((n) * 0x10)) 43 #define REG_QCSP_DD_CFG(n) (0x000c + ((n) * 0x10)) 44 #define REG_DD_CFG 0x0200 45 #define REG_DCP_CFG(n) (0x0300 + ((n) * 0x10)) 46 #define REG_DCP_DD_CFG(n) (0x0304 + ((n) * 0x10)) 47 #define REG_DCP_DLM_AVG(n) (0x030c + ((n) * 0x10)) 48 #define REG_PFDR_FPC 0x0400 49 #define REG_PFDR_FP_HEAD 0x0404 50 #define REG_PFDR_FP_TAIL 0x0408 [all …]
|
/linux-6.14.4/drivers/iommu/ |
D | fsl_pamu.h | 22 #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */ 23 #define PAMU_PE 0x40000000 /* enable PAMU */ 26 #define PAMU_OFFSET 0x1000 28 #define PAMU_MMAP_REGS_BASE 0 46 #define PAMU_POES1 0x0040 47 #define PAMU_POES2 0x0044 48 #define PAMU_POEAH 0x0048 49 #define PAMU_POEAL 0x004C 50 #define PAMU_AVS1 0x0050 51 #define PAMU_AVS1_AV 0x1 [all …]
|
/linux-6.14.4/drivers/video/fbdev/kyro/ |
D | STG4000Reg.h | 54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY 59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP 64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA, 75 /* 0h */ 76 volatile u32 Thread0Enable; /* 0x0000 */ 77 volatile u32 Thread1Enable; /* 0x0004 */ 78 volatile u32 Thread0Recover; /* 0x0008 */ 79 volatile u32 Thread1Recover; /* 0x000C */ 80 volatile u32 Thread0Step; /* 0x0010 */ 81 volatile u32 Thread1Step; /* 0x0014 */ [all …]
|
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/spl/ |
D | dc_spl_scl_filters.c | 11 // <sharpness> = 0 17 0x1000, 0x0000, 18 0x0FF0, 0x0010, 19 0x0FB0, 0x0050, 20 0x0F34, 0x00CC, 21 0x0E68, 0x0198, 22 0x0D44, 0x02BC, 23 0x0BC4, 0x043C, 24 0x09FC, 0x0604, 25 0x0800, 0x0800 [all …]
|
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_scl_filters.c | 31 // <sharpness> = 0 37 0x1000, 0x0000, 38 0x0FF0, 0x0010, 39 0x0FB0, 0x0050, 40 0x0F34, 0x00CC, 41 0x0E68, 0x0198, 42 0x0D44, 0x02BC, 43 0x0BC4, 0x043C, 44 0x09FC, 0x0604, 45 0x0800, 0x0800 [all …]
|
/linux-6.14.4/drivers/net/ethernet/freescale/enetc/ |
D | enetc_hw.h | 12 #define ENETC_DEV_ID_PF 0xe100 13 #define ENETC_DEV_ID_VF 0xef00 14 #define ENETC_DEV_ID_PTP 0xee02 17 #define ENETC_BAR_REGS 0 19 /** SI regs, offset: 0h */ 20 #define ENETC_SIMR 0 22 #define ENETC_SIMR_RSSE BIT(0) 23 #define ENETC_SICTR0 0x18 24 #define ENETC_SICTR1 0x1c 25 #define ENETC_SIPCAPR0 0x20 [all …]
|
/linux-6.14.4/include/video/ |
D | radeon.h | 6 #define RADEON_REGSIZE 0x4000 9 #define MM_INDEX 0x0000 10 #define MM_DATA 0x0004 11 #define BUS_CNTL 0x0030 12 #define HI_STAT 0x004C 13 #define BUS_CNTL1 0x0034 14 #define I2C_CNTL_1 0x0094 15 #define CNFG_CNTL 0x00E0 16 #define CNFG_MEMSIZE 0x00F8 17 #define CNFG_APER_0_BASE 0x0100 [all …]
|
/linux-6.14.4/drivers/scsi/isci/ |
D | registers.h | 66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000) 69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000) 72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800) 75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00) 78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF) 79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0) 81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT) 86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) 87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) 88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT) [all …]
|
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
D | mmhub_1_8_0_offset.h | 29 // base address: 0x60000 30 …DAGB0_RDCLI0 0x0000 31 …e regDAGB0_RDCLI0_BASE_IDX 0 32 …DAGB0_RDCLI1 0x0001 33 …e regDAGB0_RDCLI1_BASE_IDX 0 34 …DAGB0_RDCLI2 0x0002 35 …e regDAGB0_RDCLI2_BASE_IDX 0 36 …DAGB0_RDCLI3 0x0003 37 …e regDAGB0_RDCLI3_BASE_IDX 0 38 …DAGB0_RDCLI4 0x0004 [all …]
|
D | mmhub_1_7_offset.h | 29 // base address: 0x68000 30 …DAGB0_RDCLI0 0x0000 31 …e regDAGB0_RDCLI0_BASE_IDX 0 32 …DAGB0_RDCLI1 0x0001 33 …e regDAGB0_RDCLI1_BASE_IDX 0 34 …DAGB0_RDCLI2 0x0002 35 …e regDAGB0_RDCLI2_BASE_IDX 0 36 …DAGB0_RDCLI3 0x0003 37 …e regDAGB0_RDCLI3_BASE_IDX 0 38 …DAGB0_RDCLI4 0x0004 [all …]
|
/linux-6.14.4/sound/soc/mediatek/mt8186/ |
D | mt8186-reg.h | 107 #define CLEAR_FLAG_SFT 0 108 #define CLEAR_FLAG_MASK_SFT BIT(0) 153 #define AUDIO_AFE_ON_SFT 0 154 #define AUDIO_AFE_ON_MASK_SFT BIT(0) 157 #define AFE_ON_RETM_SFT 0 158 #define AFE_ON_RETM_MASK_SFT BIT(0) 187 #define I2S_EN_SFT 0 188 #define I2S_EN_MASK_SFT BIT(0) 209 #define I2S2_EN_SFT 0 210 #define I2S2_EN_MASK_SFT BIT(0) [all …]
|
/linux-6.14.4/sound/soc/mediatek/mt8192/ |
D | mt8192-reg.h | 26 #define BCK_INVERSE_MASK 0x1 27 #define BCK_INVERSE_MASK_SFT (0x1 << 3) 31 #define VUL12_ON_MASK 0x1 32 #define VUL12_ON_MASK_SFT (0x1 << 31) 34 #define MOD_DAI_ON_MASK 0x1 35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30) 37 #define DAI_ON_MASK 0x1 38 #define DAI_ON_MASK_SFT (0x1 << 29) 40 #define DAI2_ON_MASK 0x1 41 #define DAI2_ON_MASK_SFT (0x1 << 28) [all …]
|
/linux-6.14.4/fs/hfsplus/ |
D | tables.c | 24 // High-byte indices ( == 0 iff no case mapping and no ignorables ) 27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000, 28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, [all …]
|
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_12_0_offset.h | 27 // base address: 0x48 28 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012 29 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 33 // base address: 0x4c 34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014 35 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 39 // base address: 0x0 40 …DC_PERFMON0_PERFCOUNTER_CNTL 0x0020 42 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x0021 44 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022 [all …]
|