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/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8ulp-pinctrl.yaml73 reg = <0x298c0000 0x10000>;
77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt8195-apmixedsys.c17 .set_ofs = 0x8,
18 .clr_ofs = 0x8,
19 .sta_ofs = 0x8,
62 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
63 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
64 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
65 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
66 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
67 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
[all …]
/linux-6.14.4/drivers/phy/
Dphy-airoha-pcie-regs.h11 #define REG_CSR_2L_CMN 0x0000
12 #define CSR_2L_PXP_CMN_LANE_EN BIT(0)
15 #define REG_CSR_2L_JCPLL_IB_EXT 0x0004
20 #define REG_CSR_2L_JCPLL_LPF_BR 0x0008
21 #define CSR_2L_PXP_JCPLL_LPF_BR GENMASK(4, 0)
26 #define REG_CSR_2L_JCPLL_LPF_BWC 0x000c
27 #define CSR_2L_PXP_JCPLL_LPF_BWC GENMASK(4, 0)
31 #define REG_CSR_2L_JCPLL_KBAND_KFC 0x0010
32 #define CSR_2L_PXP_JCPLL_KBAND_KFC GENMASK(1, 0)
37 #define REG_CSR_2L_JCPLL_MMD_PREDIV_MODE 0x0014
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux-6.14.4/drivers/net/wireless/broadcom/b43/
Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
Dradio_2055.c24 #define B2055_INITTAB_ENTRY_OK 0x01
25 #define B2055_INITTAB_UPLOAD 0x02
31 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
32 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
33 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
34 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
35 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
36 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
37 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
38 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
[all …]
Dradio_2056.c24 #define B2056_INITTAB_ENTRY_OK 0x01
25 #define B2056_INITTAB_UPLOAD 0x02
39 [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
40 [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
41 [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
42 [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
43 [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
44 [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
45 [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
46 [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
[all …]
/linux-6.14.4/drivers/usb/core/
Dquirks.c49 quirk_count = 0; in quirks_param_set()
55 for (quirk_count = 1, i = 0; val[i]; i++) in quirks_param_set()
67 quirk_count = 0; in quirks_param_set()
73 for (i = 0, p = val; p && *p;) { in quirks_param_set()
94 for (flags = 0; *field; field++) { in quirks_param_set()
159 return 0; in quirks_param_set()
194 { USB_DEVICE(0x0204, 0x6025), .driver_info = USB_QUIRK_RESET_RESUME },
197 { USB_DEVICE(0x0218, 0x0201), .driver_info =
201 { USB_DEVICE(0x0218, 0x0401), .driver_info =
205 { USB_DEVICE(0x03f0, 0x0701), .driver_info =
[all …]
/linux-6.14.4/drivers/net/phy/
Dbcm-phy-ptp.c19 #define SLICE_CTRL 0x0810
20 #define SLICE_TX_EN BIT(0)
22 #define TX_EVENT_MODE 0x0811
23 #define MODE_TX_UPDATE_CF BIT(0)
25 #define MODE_TX_REPLACE_TS GENMASK(1, 0)
26 #define RX_EVENT_MODE 0x0819
27 #define MODE_RX_UPDATE_CF BIT(0)
29 #define MODE_RX_INSERT_TS_64 GENMASK(1, 0)
31 #define MODE_EVT_SHIFT_SYNC 0
36 #define MODE_SEL_SHIFT_PORT 0
[all …]
Dmicrochip_t1.c15 #define PHY_ID_LAN87XX 0x0007c150
16 #define PHY_ID_LAN937X 0x0007c180
17 #define PHY_ID_LAN887X 0x0007c1f0
19 #define MCHP_RDS_PTP_LTC_BASE_ADDR 0xe000
20 #define MCHP_RDS_PTP_PORT_BASE_ADDR (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800)
23 #define LAN87XX_EXT_REG_CTL (0x14)
24 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
25 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
27 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
30 #define LAN87XX_EXT_REG_RD_DATA (0x15)
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_3_3_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
Dmmhub_3_0_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_3_0_1_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
Dmmhub_1_8_0_offset.h29 // base address: 0x60000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
Dmmhub_1_7_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/linux-6.14.4/sound/soc/mediatek/mt8365/
Dmt8365-reg.h15 #define AUDIO_TOP_CON0 (0x0000)
16 #define AUDIO_TOP_CON1 (0x0004)
17 #define AUDIO_TOP_CON2 (0x0008)
18 #define AUDIO_TOP_CON3 (0x000c)
20 #define AFE_DAC_CON0 (0x0010)
21 #define AFE_DAC_CON1 (0x0014)
22 #define AFE_I2S_CON (0x0018)
23 #define AFE_CONN0 (0x0020)
24 #define AFE_CONN1 (0x0024)
25 #define AFE_CONN2 (0x0028)
[all …]
/linux-6.14.4/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_n.c28 radio_type##_##jspace##0 : \
34 radio_type##_##jspace##0 : \
42 radio_type##_##jspace##0##_##reg_name : \
47 radio_type##_##jspace##0##_##reg_name : \
53 radio_type##_##reg_name##_##jspace##0 : \
58 radio_type##_##reg_name##_##jspace##0 : \
107 #define NPHY_RSSICAL_NB_TARGET 0
120 #define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
129 #define NPHY_N_GCTL 0x66
135 #define NPHY_PAPD_COMP_OFF 0
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/spl/
Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux-6.14.4/sound/soc/mediatek/mt8195/
Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath5k/
Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/linux-6.14.4/sound/soc/mediatek/mt8188/
Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x0044)
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_offset.h28 // base address: 0x4980
29 …SDMA0_UCODE_ADDR 0x0000
30 …e regSDMA0_UCODE_ADDR_BASE_IDX 0
31 …SDMA0_UCODE_DATA 0x0001
32 …e regSDMA0_UCODE_DATA_BASE_IDX 0
33 …SDMA0_VF_ENABLE 0x000a
34 …e regSDMA0_VF_ENABLE_BASE_IDX 0
35 …SDMA0_CONTEXT_GROUP_BOUNDARY 0x0019
36 …e regSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
37 …SDMA0_POWER_CNTL 0x001a
[all …]

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