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/linux-6.14.4/fs/hfsplus/
Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux-6.14.4/arch/sh/include/mach-common/mach/
Dhighlander.h6 #define PA_NORFLASH_ADDR 0x00000000
7 #define PA_NORFLASH_SIZE 0x04000000
10 #define PA_BCR 0xa4000000 /* FPGA */
13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
16 #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
17 #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
18 #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
[all …]
/linux-6.14.4/drivers/media/rc/keymaps/
Drc-msi-digivox-ii.c12 { 0x0302, KEY_NUMERIC_2 },
13 { 0x0303, KEY_UP }, /* up */
14 { 0x0304, KEY_NUMERIC_3 },
15 { 0x0305, KEY_CHANNELDOWN },
16 { 0x0308, KEY_NUMERIC_5 },
17 { 0x0309, KEY_NUMERIC_0 },
18 { 0x030b, KEY_NUMERIC_8 },
19 { 0x030d, KEY_DOWN }, /* down */
20 { 0x0310, KEY_NUMERIC_9 },
21 { 0x0311, KEY_NUMERIC_7 },
[all …]
Drc-dvico-portable.c12 { 0x0302, KEY_SETUP }, /* Profile */
13 { 0x0343, KEY_POWER2 },
14 { 0x0306, KEY_EPG },
15 { 0x035a, KEY_BACK },
16 { 0x0305, KEY_MENU },
17 { 0x0347, KEY_INFO },
18 { 0x0301, KEY_TAB },
19 { 0x0342, KEY_PREVIOUSSONG },/* Replay */
20 { 0x0349, KEY_VOLUMEUP },
21 { 0x0309, KEY_VOLUMEDOWN },
[all …]
Drc-avermedia-m135a.c23 { 0x0200, KEY_POWER2 },
24 { 0x022e, KEY_DOT }, /* '.' */
25 { 0x0201, KEY_MODE }, /* TV/FM or SOURCE */
27 { 0x0205, KEY_NUMERIC_1 },
28 { 0x0206, KEY_NUMERIC_2 },
29 { 0x0207, KEY_NUMERIC_3 },
30 { 0x0209, KEY_NUMERIC_4 },
31 { 0x020a, KEY_NUMERIC_5 },
32 { 0x020b, KEY_NUMERIC_6 },
33 { 0x020d, KEY_NUMERIC_7 },
[all …]
/linux-6.14.4/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux-6.14.4/sound/soc/codecs/
Dmax98373-sdw.h10 #define MAX98373_R0040_SCP_INIT_STAT_1 0x0040
11 #define MAX98373_R0041_SCP_INIT_MASK_1 0x0041
12 #define MAX98373_R0042_SCP_INIT_STAT_2 0x0042
13 #define MAX98373_R0044_SCP_CTRL 0x0044
14 #define MAX98373_R0045_SCP_SYSTEM_CTRL 0x0045
15 #define MAX98373_R0046_SCP_DEV_NUMBER 0x0046
16 #define MAX98373_R0050_SCP_DEV_ID_0 0x0050
17 #define MAX98373_R0051_SCP_DEV_ID_1 0x0051
18 #define MAX98373_R0052_SCP_DEV_ID_2 0x0052
19 #define MAX98373_R0053_SCP_DEV_ID_3 0x0053
[all …]
Drt711-sdw.h12 { 0x0000, 0x00 },
13 { 0x0001, 0x00 },
14 { 0x0002, 0x00 },
15 { 0x0003, 0x00 },
16 { 0x0004, 0x00 },
17 { 0x0005, 0x01 },
18 { 0x0020, 0x00 },
19 { 0x0022, 0x00 },
20 { 0x0023, 0x00 },
21 { 0x0024, 0x00 },
[all …]
Drt1015.h17 #define RT1015_DEVICE_ID_VAL 0x1011
18 #define RT1015_DEVICE_ID_VAL2 0x1015
20 #define RT1015_RESET 0x0000
21 #define RT1015_CLK2 0x0004
22 #define RT1015_CLK3 0x0006
23 #define RT1015_PLL1 0x000a
24 #define RT1015_PLL2 0x000c
25 #define RT1015_DUM_RW1 0x000e
26 #define RT1015_DUM_RW2 0x0010
27 #define RT1015_DUM_RW3 0x0012
[all …]
/linux-6.14.4/drivers/mtd/devices/
Dbcm47xxsflash.h10 #define OPCODE_ST_WREN 0x0006 /* Write Enable */
11 #define OPCODE_ST_WRDIS 0x0004 /* Write Disable */
12 #define OPCODE_ST_RDSR 0x0105 /* Read Status Register */
13 #define OPCODE_ST_WRSR 0x0101 /* Write Status Register */
14 #define OPCODE_ST_READ 0x0303 /* Read Data Bytes */
15 #define OPCODE_ST_PP 0x0302 /* Page Program */
16 #define OPCODE_ST_SE 0x02d8 /* Sector Erase */
17 #define OPCODE_ST_BE 0x00c7 /* Bulk Erase */
18 #define OPCODE_ST_DP 0x00b9 /* Deep Power-down */
19 #define OPCODE_ST_RES 0x03ab /* Read Electronic Signature */
[all …]
/linux-6.14.4/include/linux/mmc/
Dsdio_ids.h13 #define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */
14 #define SDIO_CLASS_UART 0x01 /* standard UART interface */
15 #define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */
16 #define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */
17 #define SDIO_CLASS_GPS 0x04 /* GPS standard interface */
18 #define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */
19 #define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
20 #define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
21 #define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
22 #define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_6_0_d.h26 #define ixLCAC_MC0_CNTL 0x011C
27 #define ixLCAC_MC0_OVR_SEL 0x011D
28 #define ixLCAC_MC0_OVR_VAL 0x011E
29 #define ixLCAC_MC1_CNTL 0x011F
30 #define ixLCAC_MC1_OVR_SEL 0x0120
31 #define ixLCAC_MC1_OVR_VAL 0x0121
32 #define ixLCAC_MC2_CNTL 0x0122
33 #define ixLCAC_MC2_OVR_SEL 0x0123
34 #define ixLCAC_MC2_OVR_VAL 0x0124
35 #define ixLCAC_MC3_CNTL 0x0125
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
Dl2_cache.json43 "EventCode": "0x0300",
48 "EventCode": "0x0301",
53 "EventCode": "0x0302",
58 "EventCode": "0x0305",
63 "EventCode": "0x0308",
68 "EventCode": "0x0309",
73 "EventCode": "0x030A",
78 "EventCode": "0x030B",
83 "EventCode": "0x030C",
88 "EventCode": "0x030D",
[all …]
/linux-6.14.4/drivers/media/usb/gspca/
Dzc3xx-reg.h12 #define ZC3XX_R000_SYSTEMCONTROL 0x0000
13 #define ZC3XX_R001_SYSTEMOPERATING 0x0001
16 #define ZC3XX_R002_CLOCKSELECT 0x0002
17 #define ZC3XX_R003_FRAMEWIDTHHIGH 0x0003
18 #define ZC3XX_R004_FRAMEWIDTHLOW 0x0004
19 #define ZC3XX_R005_FRAMEHEIGHTHIGH 0x0005
20 #define ZC3XX_R006_FRAMEHEIGHTLOW 0x0006
23 #define ZC3XX_R008_CLOCKSETTING 0x0008
26 #define ZC3XX_R00B_TESTMODECONTROL 0x000b
29 #define ZC3XX_R00C_LASTACQTIME 0x000c
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux-6.14.4/drivers/gpu/drm/panel/
Dpanel-lg-lb035q02.c47 buffer[0] = 0x70; in lb035q02_write()
48 buffer[1] = 0x00; in lb035q02_write()
49 buffer[2] = reg & 0x7f; in lb035q02_write()
54 buffer[4] = 0x72; in lb035q02_write()
70 { 0x01, 0x6300 }, in lb035q02_init()
71 { 0x02, 0x0200 }, in lb035q02_init()
72 { 0x03, 0x0177 }, in lb035q02_init()
73 { 0x04, 0x04c7 }, in lb035q02_init()
74 { 0x05, 0xffc0 }, in lb035q02_init()
75 { 0x06, 0xe806 }, in lb035q02_init()
[all …]
/linux-6.14.4/include/linux/mfd/mt6397/
Dregisters.h11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
/linux-6.14.4/drivers/video/fbdev/omap2/omapfb/displays/
Dpanel-lgphilips-lb035q02.c69 buffer[0] = 0x70; in lb035q02_write_reg()
70 buffer[1] = 0x00; in lb035q02_write_reg()
71 buffer[2] = reg & 0x7f; in lb035q02_write_reg()
76 buffer[4] = 0x72; in lb035q02_write_reg()
88 lb035q02_write_reg(spi, 0x01, 0x6300); in init_lb035q02_panel()
89 lb035q02_write_reg(spi, 0x02, 0x0200); in init_lb035q02_panel()
90 lb035q02_write_reg(spi, 0x03, 0x0177); in init_lb035q02_panel()
91 lb035q02_write_reg(spi, 0x04, 0x04c7); in init_lb035q02_panel()
92 lb035q02_write_reg(spi, 0x05, 0xffc0); in init_lb035q02_panel()
93 lb035q02_write_reg(spi, 0x06, 0xe806); in init_lb035q02_panel()
[all …]
/linux-6.14.4/drivers/media/i2c/
Dov8856.c26 #define OV8856_REG_CHIP_ID 0x300a
27 #define OV8856_CHIP_ID 0x00885a
29 #define OV8856_REG_MODE_SELECT 0x0100
30 #define OV8856_MODE_STANDBY 0x00
31 #define OV8856_MODE_STREAMING 0x01
34 #define OV8856_2A_MODULE 0x01
35 #define OV8856_1B_MODULE 0x02
37 /* the OTP read-out buffer is at 0x7000 and 0xf is the offset
40 #define OV8856_MODULE_REVISION 0x700f
41 #define OV8856_OTP_MODE_CTRL 0x3d84
[all …]
/linux-6.14.4/include/linux/mfd/mt6323/
Dregisters.h10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
/linux-6.14.4/drivers/soc/fsl/qbman/
Dqman_priv.h44 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
101 #define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f))
110 memset(c, 0, sizeof(*c)); in qman_cgrs_init()
115 memset(c, 0xff, sizeof(*c)); in qman_cgrs_fill()
137 for (ret = 0; ret < 8; ret++) in qman_cgrs_and()
149 for (ret = 0; ret < 8; ret++) in qman_cgrs_xor()
181 #define QMAN_REV11 0x0101
182 #define QMAN_REV12 0x0102
183 #define QMAN_REV20 0x0200
184 #define QMAN_REV30 0x0300
[all …]
/linux-6.14.4/drivers/usb/misc/
Dappledisplay.c21 #define APPLE_VENDOR_ID 0x05AC
23 #define USB_REQ_GET_REPORT 0x01
24 #define USB_REQ_SET_REPORT 0x09
28 #define ACD_USB_EDID 0x0302
29 #define ACD_USB_BRIGHTNESS 0x0310
31 #define ACD_BTN_NONE 0
45 .bInterfaceProtocol = 0x00
49 { APPLEDISPLAY_DEVICE(0x9218) },
50 { APPLEDISPLAY_DEVICE(0x9219) },
51 { APPLEDISPLAY_DEVICE(0x921c) },
[all …]
/linux-6.14.4/arch/powerpc/platforms/44x/
Dpci.h18 #define PCIX0_VENDID 0x000
19 #define PCIX0_DEVID 0x002
20 #define PCIX0_COMMAND 0x004
21 #define PCIX0_STATUS 0x006
22 #define PCIX0_REVID 0x008
23 #define PCIX0_CLS 0x009
24 #define PCIX0_CACHELS 0x00c
25 #define PCIX0_LATTIM 0x00d
26 #define PCIX0_HDTYPE 0x00e
27 #define PCIX0_BIST 0x00f
[all …]
/linux-6.14.4/include/linux/
Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux-6.14.4/include/sound/
Dopl3.h11 * The OPL-3 mode is switched on by writing 0x01, to the offset 5
24 * For example setting the rightmost bit (0x01) changes the
34 * register of the voice (0xC0-0xC8). In 4 OP voices these bits are
51 #define OPL3_REG_TEST 0x01
52 #define OPL3_ENABLE_WAVE_SELECT 0x20
54 #define OPL3_REG_TIMER1 0x02
55 #define OPL3_REG_TIMER2 0x03
56 #define OPL3_REG_TIMER_CONTROL 0x04 /* Left side */
57 #define OPL3_IRQ_RESET 0x80
58 #define OPL3_TIMER1_MASK 0x40
[all …]

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