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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra210-pinmux.yaml122 reg = <0x700008d4 0x02a8>, /* Pad control registers */
123 <0x70003000 0x1000>; /* Mux registers */
126 pinctrl-0 = <&state_boot>;
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/linux-6.14.4/drivers/net/can/spi/mcp251xfd/
Dmcp251xfd-crc16.c24 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011,
25 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022,
26 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072,
27 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041,
28 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2,
29 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1,
30 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1,
31 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082,
32 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192,
33 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1,
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_d.h26 #define ixCLIENT0_BM 0x0220
27 #define ixCLIENT0_CD0 0x0210
28 #define ixCLIENT0_CD1 0x0214
29 #define ixCLIENT0_CD2 0x0218
30 #define ixCLIENT0_CD3 0x021C
31 #define ixCLIENT0_CK0 0x0200
32 #define ixCLIENT0_CK1 0x0204
33 #define ixCLIENT0_CK2 0x0208
34 #define ixCLIENT0_CK3 0x020C
35 #define ixCLIENT0_K0 0x01F0
[all …]
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt8183-apmixedsys.c19 .set_ofs = 0x20,
20 .clr_ofs = 0x20,
21 .sta_ofs = 0x20,
29 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
93 { .div = 0, .freq = MT8183_PLL_FMAX },
102 { .div = 0, .freq = MT8183_PLL_FMAX },
111 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
112 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
113 0x0204, 0, 0, armpll_div_table),
114 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
[all …]
/linux-6.14.4/include/linux/mfd/mt6397/
Dregisters.h11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_14_0_0_offset.h28 // base address: 0x0
29 …MP1_SMN_C2PMSG_0 0x0240
30 …e regMP1_SMN_C2PMSG_0_BASE_IDX 0
31 …MP1_SMN_C2PMSG_1 0x0241
32 …e regMP1_SMN_C2PMSG_1_BASE_IDX 0
33 …MP1_SMN_C2PMSG_2 0x0242
34 …e regMP1_SMN_C2PMSG_2_BASE_IDX 0
35 …MP1_SMN_C2PMSG_3 0x0243
36 …e regMP1_SMN_C2PMSG_3_BASE_IDX 0
37 …MP1_SMN_C2PMSG_4 0x0244
[all …]
Dmp_13_0_8_offset.h31 // base address: 0x0
32 …MP0_SMN_C2PMSG_32 0x0060
33 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
34 …MP0_SMN_C2PMSG_33 0x0061
35 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
36 …MP0_SMN_C2PMSG_34 0x0062
37 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
38 …MP0_SMN_C2PMSG_35 0x0063
39 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
40 …MP0_SMN_C2PMSG_36 0x0064
[all …]
Dmp_11_5_0_offset.h27 // base address: 0x0
28 …MP0_SMN_C2PMSG_32 0x0060
29 …ne mmMP0_SMN_C2PMSG_32_BASE_IDX 0
30 …MP0_SMN_C2PMSG_33 0x0061
31 …ne mmMP0_SMN_C2PMSG_33_BASE_IDX 0
32 …MP0_SMN_C2PMSG_34 0x0062
33 …ne mmMP0_SMN_C2PMSG_34_BASE_IDX 0
34 …MP0_SMN_C2PMSG_35 0x0063
35 …ne mmMP0_SMN_C2PMSG_35_BASE_IDX 0
36 …MP0_SMN_C2PMSG_36 0x0064
[all …]
Dmp_13_0_0_offset.h28 // base address: 0x0
29 …MP0_SMN_C2PMSG_32 0x0060
30 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
31 …MP0_SMN_C2PMSG_33 0x0061
32 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
33 …MP0_SMN_C2PMSG_34 0x0062
34 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
35 …MP0_SMN_C2PMSG_35 0x0063
36 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
37 …MP0_SMN_C2PMSG_36 0x0064
[all …]
Dmp_13_0_6_offset.h29 // base address: 0x0
30 …MP0_SMN_C2PMSG_32 0x0060
31 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
32 …MP0_SMN_C2PMSG_33 0x0061
33 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
34 …MP0_SMN_C2PMSG_34 0x0062
35 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
36 …MP0_SMN_C2PMSG_35 0x0063
37 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
38 …MP0_SMN_C2PMSG_36 0x0064
[all …]
Dmp_13_0_5_offset.h30 // base address: 0x0
31 …MP0_SMN_C2PMSG_32 0x0060
32 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
33 …MP0_SMN_C2PMSG_33 0x0061
34 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
35 …MP0_SMN_C2PMSG_34 0x0062
36 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
37 …MP0_SMN_C2PMSG_35 0x0063
38 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
39 …MP0_SMN_C2PMSG_36 0x0064
[all …]
/linux-6.14.4/drivers/media/platform/ti/vpe/
Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/linux-6.14.4/drivers/media/i2c/
Dalvium-csi2.h29 #define REG_BCRM_MINOR_VERSION_R CCI_REG16(0x0000)
30 #define REG_BCRM_MAJOR_VERSION_R CCI_REG16(0x0002)
31 #define REG_BCRM_REG_ADDR_R CCI_REG16(0x0014)
33 #define REG_BCRM_FEATURE_INQUIRY_R REG_BCRM_V4L2_64BIT(0x0008)
34 #define REG_BCRM_DEVICE_FW REG_BCRM_V4L2_64BIT(0x0010)
35 #define REG_BCRM_WRITE_HANDSHAKE_RW REG_BCRM_V4L2_8BIT(0x0018)
38 #define REG_BCRM_SUPPORTED_CSI2_LANE_COUNTS_R REG_BCRM_V4L2_8BIT(0x0040)
39 #define REG_BCRM_CSI2_LANE_COUNT_RW REG_BCRM_V4L2_8BIT(0x0044)
40 #define REG_BCRM_CSI2_CLOCK_MIN_R REG_BCRM_V4L2_32BIT(0x0048)
41 #define REG_BCRM_CSI2_CLOCK_MAX_R REG_BCRM_V4L2_32BIT(0x004c)
[all …]
/linux-6.14.4/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux-6.14.4/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/linux-6.14.4/drivers/memory/
Demif.h20 #define DDR_VOLTAGE_STABLE 0
24 #define EMIF_NORMAL_TIMINGS 0
55 #define ZQ_DUALCALEN_DISABLE 0
63 #define DPD_DISABLE 0
76 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
77 #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
78 #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
79 #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
82 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
92 #define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
[all …]
/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-am642-phyboard-electra-rdk.dts45 pinctrl-0 = <&can_tc1_pins_default>;
46 #phy-cells = <0>;
54 pinctrl-0 = <&can_tc2_pins_default>;
55 #phy-cells = <0>;
64 pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
67 interrupts = <24 0 2>, <25 1 3>;
78 dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
79 <&main_pktdma 0xc101 15>, /* egress slice 0 */
80 <&main_pktdma 0xc102 15>, /* egress slice 0 */
81 <&main_pktdma 0xc103 15>, /* egress slice 0 */
[all …]
/linux-6.14.4/include/linux/mfd/mt6328/
Dregisters.h10 #define MT6328_STRUP_CON0 0x0000
11 #define MT6328_STRUP_CON2 0x0002
12 #define MT6328_STRUP_CON3 0x0004
13 #define MT6328_STRUP_CON4 0x0006
14 #define MT6328_STRUP_CON5 0x0008
15 #define MT6328_STRUP_CON6 0x000a
16 #define MT6328_STRUP_CON7 0x000c
17 #define MT6328_STRUP_CON8 0x000e
18 #define MT6328_STRUP_CON9 0x0010
19 #define MT6328_STRUP_CON10 0x0012
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/spl/
Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]

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