Searched +full:0 +full:x02040000 (Results 1 – 10 of 10) sorted by relevance
48 default: 0xffff49 minimum: 050 maximum: 0xffffff56 default: 0xfff57 minimum: 058 maximum: 0xffffffff85 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;92 pinctrl-0 = <&pinctrl_tsc>;94 measure-delay-time = <0xfff>;95 pre-charge-time = <0xffff>;
27 #size-cells = <0>;29 cpu0: cpu@0 {31 reg = <0>;45 #clock-cells = <0>;66 reg = <0x02040000 0x1000>;67 arm,data-latency = <2 2 0>;76 reg = <0x02000000 0x1000>,77 <0x02002000 0x1000>;86 reg = <0x0200a000 0x100>;88 cpu-offset = <0x80000>;[all …]
19 dcr-parent = <&{/cpus/cpu@0}>;29 #size-cells = <0>;31 cpu@0 {34 reg = <0x0>;35 clock-frequency = <0>; /* Filled in by cuboot */36 timebase-frequency = <0>; /* Filled in by cuboot */48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by55 #clock-cells = <0>;62 #address-cells = <0>;63 #size-cells = <0>;[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;108 #clock-cells = <0>;115 #clock-cells = <0>;122 #clock-cells = <0>;123 clock-frequency = <0>;129 #clock-cells = <0>;130 clock-frequency = <0>;149 reg = <0x00900000 0x20000>;[all …]
59 #clock-cells = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;78 #size-cells = <0>;83 lvds-channel@0 {85 #size-cells = <0>;86 reg = <0>;89 port@0 {90 reg = <0>;[all …]
13 #clock-cells = <0>;15 clock-frequency = <0>;22 reg = <0x0 0x70000000 0x0 0x400000>;25 ranges = <0x0 0x0 0x70000000 0x400000>;27 atf-sram@0 {28 reg = <0x0 0x20000>;32 reg = <0x1f0000 0x10000>;36 reg = <0x200000 0x200000>;42 reg = <0x00 0x00104000 0x00 0x18000>;45 ranges = <0x00 0x00 0x00104000 0x18000>;[all …]
16 #clock-cells = <0>;30 reg = <0x00 0x70000000 0x00 0x800000>;33 ranges = <0x00 0x00 0x70000000 0x800000>;35 atf-sram@0 {36 reg = <0x00 0x20000>;40 reg = <0x1f0000 0x10000>;44 reg = <0x200000 0x200000>;50 reg = <0x00 0x00100000 0x00 0x1c000>;53 ranges = <0x00 0x00 0x00100000 0x1c000>;57 reg = <0x4034 0x4>;[all …]
28 #define regSDMA0_DEC_START_DEFAULT 0x0000000029 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x0000000030 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x0000000031 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x0000000032 #define regSDMA0_POWER_CNTL_DEFAULT 0x0000000033 #define regSDMA0_CNTL_DEFAULT 0x0000244034 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d18635 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x0000054536 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x0000054537 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000[all …]
26 #define mmSDMA0_DEC_START_DEFAULT 0x0000000027 #define mmSDMA0_PG_CNTL_DEFAULT 0x0000000028 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x0000000029 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x0000000030 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x0000000031 #define mmSDMA0_POWER_CNTL_DEFAULT 0x4000005032 #define mmSDMA0_CLK_CTRL_DEFAULT 0x0000010033 #define mmSDMA0_CNTL_DEFAULT 0x000000c234 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af010735 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044[all …]
27 #define mmSDMA0_DEC_START_DEFAULT 0x0000000028 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x0000000029 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x0000000030 #define mmSDMA0_PG_CNTL_DEFAULT 0x0000000031 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x0000000032 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x0000000033 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x0000000034 #define mmSDMA0_POWER_CNTL_DEFAULT 0x4000005035 #define mmSDMA0_CLK_CTRL_DEFAULT 0x0000010036 #define mmSDMA0_CNTL_DEFAULT 0x000000c2[all …]