Searched +full:0 +full:x01c40000 (Results 1 – 14 of 14) sorted by relevance
27 #define DA8XX_TPCC_BASE 0x01c0000028 #define DA8XX_TPTC0_BASE 0x01c0800029 #define DA8XX_TPTC1_BASE 0x01c0840030 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */31 #define DA8XX_I2C0_BASE 0x01c2200032 #define DA8XX_RTC_BASE 0x01c2300033 #define DA8XX_PRUSS_MEM_BASE 0x01c3000034 #define DA8XX_MMCSD0_BASE 0x01c4000035 #define DA8XX_SPI0_BASE 0x01c4100036 #define DA830_SPI1_BASE 0x01e12000[all …]
123 reg = <0x7000000 0x10000>;134 reg = <0x01c40000 0x10000>;
76 - pp0 # Pixel Processor X interrupt (X from 0 to 7)77 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)162 reg = <0x01c40000 0x10000>;
72 #size-cells = <0>;74 cpu0: cpu@0 {77 reg = <0>;155 reg = <0x01400000 0x20000>;168 reg = <0x01c00000 0x1000>;175 reg = <0x01d00000 0x80000>;178 ranges = <0 0x01d00000 0x80000>;180 ve_sram: sram-section@0 {183 reg = <0x000000 0x80000>;190 reg = <0x01c0e000 0x1000>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
91 #size-cells = <0>;93 cpu0: cpu@0 {96 reg = <0>;112 #clock-cells = <0>;120 #clock-cells = <0>;136 reg = <0x01c00000 0x30>;143 reg = <0x01d00000 0x80000>;146 ranges = <0 0x01d00000 0x80000>;148 ve_sram: sram-section@0 {151 reg = <0x000000 0x80000>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
64 #clock-cells = <0>;72 #clock-cells = <0>;82 #size-cells = <0>;84 cpu0: cpu@0 {87 reg = <0>;130 polling-delay-passive = <0>;131 polling-delay = <0>;132 thermal-sensors = <&ths 0>;143 hysteresis = <0>;161 polling-delay-passive = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
24 #clock-cells = <0>;30 #clock-cells = <0>;38 #size-cells = <0>;40 cpu0: cpu@0 {43 reg = <0x0 0x0>;57 reg = <0x0 0x1>;66 reg = <0x0 0x2>;75 reg = <0x0 0x3>;84 reg = <0x0 0x100>;98 reg = <0x0 0x101>;[all …]
31 #clock-cells = <0>;37 #clock-cells = <0>;43 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x0 0x0>;49 clocks = <&cpufreq_hw 0>;54 qcom,freq-domain = <&cpufreq_hw 0>;67 reg = <0x0 0x1>;68 clocks = <&cpufreq_hw 0>;73 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
27 #clock-cells = <0>;33 #clock-cells = <0>;39 #size-cells = <0>;41 cpu0: cpu@0 {44 reg = <0x0 0x0>;45 clocks = <&cpufreq_hw 0>;48 qcom,freq-domain = <&cpufreq_hw 0>;70 reg = <0x0 0x100>;71 clocks = <&cpufreq_hw 0>;74 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
33 #clock-cells = <0>;38 #clock-cells = <0>;44 #size-cells = <0>;46 cpu0: cpu@0 {49 reg = <0x0 0x0>;50 clocks = <&cpufreq_hw 0>;55 qcom,freq-domain = <&cpufreq_hw 0>;68 reg = <0x0 0x1>;69 clocks = <&cpufreq_hw 0>;74 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;57 i-cache-size = <0x8000>;60 d-cache-size = <0x8000>;74 i-cache-size = <0x8000>;77 d-cache-size = <0x8000>;91 i-cache-size = <0x8000>;94 d-cache-size = <0x8000>;108 i-cache-size = <0x8000>;[all …]