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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dallwinner,sun4i-a10-nand.yaml55 minimum: 0
74 minimum: 0
97 reg = <0x01c03000 0x1000>;
106 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
108 #size-cells = <0>;
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dqcom,pcie-sa8775p.yaml91 reg = <0x0 0x01c00000 0x0 0x3000>,
92 <0x0 0x40000000 0x0 0xf20>,
93 <0x0 0x40000f20 0x0 0xa8>,
94 <0x0 0x40001000 0x0 0x4000>,
95 <0x0 0x40100000 0x0 0x100000>,
96 <0x0 0x01c03000 0x0 0x1000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
99 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
[all …]
Dqcom,pcie-sm8250.yaml102 reg = <0 0x01c00000 0 0x3000>,
103 <0 0x60000000 0 0xf1d>,
104 <0 0x60000f20 0 0xa8>,
105 <0 0x60001000 0 0x1000>,
106 <0 0x60100000 0 0x100000>,
107 <0 0x01c03000 0 0x1000>;
109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
[all …]
Dqcom,pcie-ep.yaml247 reg = <0x01c00000 0x3000>,
248 <0x40000000 0xf1d>,
249 <0x40000f20 0xc8>,
250 <0x40001000 0x1000>,
251 <0x40002000 0x1000>,
252 <0x01c03000 0x3000>;
266 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
283 linux,pci-domain = <0>;
/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/allwinner/
Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsa8775p.dtsi30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
89 reg = <0x0 0x200>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 cpu0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
[all …]
Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]