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/linux-6.14.4/Documentation/devicetree/bindings/interconnect/
Dqcom,sm8450-rpmh.yaml83 - description: aggre-NOC PCIe 0 AXI clock
109 interconnect-0 {
117 reg = <0x01700000 0x31080>;
/linux-6.14.4/arch/powerpc/boot/dts/
Dbluestone.dts16 dcr-parent = <&{/cpus/cpu@0}>;
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
/linux-6.14.4/arch/m68k/ifpsp060/
Dfpsp.sa1 .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000
2 .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000
3 .long 0x60ff0000,0x1b100000,0x60ff0000,0x19aa0000
4 .long 0x60ff0000,0x1b5a0000,0x60ff0000,0x062e0000
5 .long 0x60ff0000,0x102c0000,0x51fc51fc,0x51fc51fc
6 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
7 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
8 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
9 .long 0x2f00203a,0xff2c487b,0x0930ffff,0xfef8202f
10 .long 0x00044e74,0x00042f00,0x203afef2,0x487b0930
[all …]
/linux-6.14.4/drivers/remoteproc/
Dqcom_q6v5_wcss.c28 #define Q6SS_RESET_REG 0x014
29 #define Q6SS_GFMUX_CTL_REG 0x020
30 #define Q6SS_PWR_CTL_REG 0x030
31 #define Q6SS_MEM_PWR_CTL 0x0B0
32 #define Q6SS_STRAP_ACC 0x110
33 #define Q6SS_CGC_OVERRIDE 0x034
34 #define Q6SS_BCR_REG 0x6000
37 #define AXI_HALTREQ_REG 0x0
38 #define AXI_HALTACK_REG 0x4
39 #define AXI_IDLE_REG 0x8
[all …]
/linux-6.14.4/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/allwinner/
Dsun9i-a80.dtsi65 #size-cells = <0>;
67 cpu0: cpu@0 {
73 reg = <0x0>;
82 reg = <0x1>;
91 reg = <0x2>;
100 reg = <0x3>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
[all …]
Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsdm670.dtsi35 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0 0x0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8750.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0 0x0>;
46 reg = <0x0 0x100>;
56 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
76 reg = <0x0 0x400>;
86 reg = <0x0 0x500>;
96 reg = <0x0 0x10000>;
112 reg = <0x0 0x10100>;
[all …]
Dqcs8300.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0 0x0>;
66 reg = <0x0 0x100>;
85 reg = <0x0 0x200>;
104 reg = <0x0 0x300>;
123 reg = <0x0 0x10000>;
142 reg = <0x0 0x10100>;
[all …]
Dqcs615.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0 0x0>;
48 reg = <0x0 0x100>;
67 reg = <0x0 0x200>;
86 reg = <0x0 0x300>;
105 reg = <0x0 0x400>;
124 reg = <0x0 0x500>;
143 reg = <0x0 0x600>;
163 reg = <0x0 0x700>;
[all …]
Dsm6350.dtsi32 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8180x.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8550.dtsi39 #clock-cells = <0>;
44 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0 0>;
72 clocks = <&cpufreq_hw 0>;
77 qcom,freq-domain = <&cpufreq_hw 0>;
97 reg = <0 0x100>;
[all …]
Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]
Dsdm845.dtsi78 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #size-cells = <0>;
94 cpu0: cpu@0 {
97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 0>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 cpu0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
[all …]
Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
/linux-6.14.4/drivers/soc/tegra/cbb/
Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]