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/linux-6.14.4/Documentation/devicetree/bindings/crypto/
Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <[email protected]>'
12 - Pankaj Gupta <[email protected]>
13 - Gaurav Jain <[email protected]>
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
40 - items:
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/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.2-job-ring",
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Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
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Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
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Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
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Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
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Dp1023si-post.dtsi4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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/linux-6.14.4/drivers/crypto/caam/
Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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/linux-6.14.4/drivers/clk/imx/
Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define CCM_MPCTL 0x00
21 #define CCM_UPCTL 0x04
22 #define CCM_CCTL 0x08
23 #define CCM_CGCR0 0x0C
24 #define CCM_CGCR1 0x10
25 #define CCM_CGCR2 0x14
26 #define CCM_PCDR0 0x18
27 #define CCM_PCDR1 0x1C
28 #define CCM_PCDR2 0x20
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/linux-6.14.4/drivers/clk/samsung/
Dclk-exynos5420.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
21 #define APLL_LOCK 0x0
22 #define APLL_CON0 0x100
23 #define SRC_CPU 0x200
24 #define DIV_CPU0 0x500
25 #define DIV_CPU1 0x504
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