| /linux-6.14.4/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_job.c | 37 struct amdgpu_job *job) in amdgpu_job_do_core_dump() argument
41 dev_info(adev->dev, "Dumping IP State\n"); in amdgpu_job_do_core_dump()
42 for (i = 0; i < adev->num_ip_blocks; i++) in amdgpu_job_do_core_dump()
43 if (adev->ip_blocks[i].version->funcs->dump_ip_state) in amdgpu_job_do_core_dump()
44 adev->ip_blocks[i].version->funcs in amdgpu_job_do_core_dump()
45 ->dump_ip_state((void *)&adev->ip_blocks[i]); in amdgpu_job_do_core_dump()
46 dev_info(adev->dev, "Dumping IP State Completed\n"); in amdgpu_job_do_core_dump()
48 amdgpu_coredump(adev, true, false, job); in amdgpu_job_do_core_dump()
52 struct amdgpu_job *job) in amdgpu_job_core_dump() argument
61 mutex_lock(&hive->hive_lock); in amdgpu_job_core_dump()
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| D | amdgpu_ib.c | 45 * command ring and the hw will fetch the commands from the IB
48 * put in IBs for execution by the requested ring.
52 * amdgpu_ib_get - request an IB (Indirect Buffer)
62 * Returns 0 on success, error on failure.
71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], in amdgpu_ib_get()
72 &ib->sa_bo, size); in amdgpu_ib_get()
74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); in amdgpu_ib_get()
78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); in amdgpu_ib_get()
80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; in amdgpu_ib_get()
83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); in amdgpu_ib_get()
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| D | amdgpu_ids.c | 26 #include <linux/dma-fence-array.h>
50 * amdgpu_pasid_alloc - Allocate a PASID
56 * Returns a positive integer on success. Returns %-EINVAL if bits==0.
57 * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
62 int pasid = -EINVAL; in amdgpu_pasid_alloc()
64 for (bits = min(bits, 31U); bits > 0; bits--) { in amdgpu_pasid_alloc()
65 pasid = ida_alloc_range(&amdgpu_pasid_ida, 1U << (bits - 1), in amdgpu_pasid_alloc()
66 (1U << bits) - 1, GFP_KERNEL); in amdgpu_pasid_alloc()
67 if (pasid != -ENOSPC) in amdgpu_pasid_alloc()
71 if (pasid >= 0) in amdgpu_pasid_alloc()
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| D | amdgpu_fence.c | 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
48 * are no longer in use by the associated ring on the GPU and
56 struct amdgpu_ring *ring; member
66 return -ENOMEM; in amdgpu_fence_slab_init()
67 return 0; in amdgpu_fence_slab_init()
84 if (__f->base.ops == &amdgpu_fence_ops || in to_amdgpu_fence()
85 __f->base.ops == &amdgpu_job_fence_ops) in to_amdgpu_fence()
92 * amdgpu_fence_write - write a fence value
94 * @ring: ring the fence is associated with
99 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) in amdgpu_fence_write() argument
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| D | amdgpu_trace.h | 35 #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \ argument
36 job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
47 __entry->did = did;
48 __entry->reg = reg;
49 __entry->value = value;
51 TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
52 (unsigned long)__entry->did,
53 (unsigned long)__entry->reg,
54 (unsigned long)__entry->value)
66 __entry->did = did;
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| D | amdgpu_ring.h | 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
92 /* Direct submission to the ring buffer during init and reset. */
117 /* sync_seq is protected by ring emission lock */
131 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
132 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
133 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
135 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
136 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
143 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
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| D | amdgpu_vce.c | 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
85 static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
87 static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
91 * amdgpu_vce_sw_init - allocate memory, load vce firmware
105 switch (adev->asic_type) { in amdgpu_vce_sw_init()
158 return -EINVAL; in amdgpu_vce_sw_init()
161 r = amdgpu_ucode_request(adev, &adev->vce.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name); in amdgpu_vce_sw_init()
163 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n", in amdgpu_vce_sw_init()
165 amdgpu_ucode_release(&adev->vce.fw); in amdgpu_vce_sw_init()
169 hdr = (const struct common_firmware_header *)adev->vce.fw->data; in amdgpu_vce_sw_init()
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| D | uvd_v7_0.c | 44 …UVD_PG0_CC_UVD_HARVESTING 0x00c7
47 …0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
48 …_HARVESTING__UVD_DISABLE_MASK 0x00000002L
65 * uvd_v7_0_ring_get_rptr - get read pointer
67 * @ring: amdgpu_ring pointer
71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v7_0_ring_get_rptr() argument
73 struct amdgpu_device *adev = ring->adev; in uvd_v7_0_ring_get_rptr()
75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
81 * @ring: amdgpu_ring pointer
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| D | uvd_v6_0.c | 57 * uvd_v6_0_enc_support - get encode support status
65 return ((adev->asic_type >= CHIP_POLARIS10) && in uvd_v6_0_enc_support()
66 (adev->asic_type <= CHIP_VEGAM) && in uvd_v6_0_enc_support()
67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); in uvd_v6_0_enc_support()
71 * uvd_v6_0_ring_get_rptr - get read pointer
73 * @ring: amdgpu_ring pointer
77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v6_0_ring_get_rptr() argument
79 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_get_rptr()
85 * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
87 * @ring: amdgpu_ring pointer
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| D | amdgpu_vcn.c | 2 * Copyright 2016-2024 Advanced Micro Devices, Inc.
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
102 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_early_init()
103 if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) in amdgpu_vcn_early_init()
104 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, in amdgpu_vcn_early_init()
108 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, in amdgpu_vcn_early_init()
112 amdgpu_ucode_release(&adev->vcn.inst[i].fw); in amdgpu_vcn_early_init()
127 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); in amdgpu_vcn_sw_init()
128 mutex_init(&adev->vcn.vcn_pg_lock); in amdgpu_vcn_sw_init()
129 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); in amdgpu_vcn_sw_init()
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| /linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | raideng.txt | 3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
13 major number whereas 0 represents minor number. The
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 reg = <0x320000 0x10000>;
26 ranges = <0 0x320000 0x10000>;
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| /linux-6.14.4/Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec6.txt | 4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
20 - compatible
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
31 - #address-cells
37 - #size-cells
44 - reg
46 Value type: <prop-encoded-array>
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| D | fsl,sec-v4.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <[email protected]>'
12 - Pankaj Gupta <[email protected]>
13 - Gaurav Jain <[email protected]>
21 2. Job Rings (HW interface between cores & SEC 4 registers).
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
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| /linux-6.14.4/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-sec6.0-0.dtsi | 35 compatible = "fsl,sec-v6.0", "fsl,sec-v5.0",
36 "fsl,sec-v4.0";
37 fsl,sec-era = <6>;
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "fsl,sec-v6.0-job-ring",
43 "fsl,sec-v5.2-job-ring",
44 "fsl,sec-v5.0-job-ring",
45 "fsl,sec-v4.4-job-ring",
46 "fsl,sec-v4.0-job-ring";
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| D | qoriq-sec5.2-0.dtsi | 2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.2-job-ring",
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| D | qoriq-sec5.3-0.dtsi | 2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
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| D | pq3-sec4.4-0.dtsi | 2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges = <0x0 0x30000 0x10000>;
41 reg = <0x30000 0x10000>;
42 interrupts = <58 2 0 0>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
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| D | qoriq-sec5.0-0.dtsi | 2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
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| D | qoriq-sec4.2-0.dtsi | 2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
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| D | qoriq-raid1.0-0.dtsi | 2 * QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ]
36 compatible = "fsl,raideng-v1.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x320000 0x10000>;
40 ranges = <0 0x320000 0x10000>;
43 compatible = "fsl,raideng-v1.0-job-queue";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 reg = <0x1000 0x1000>;
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| /linux-6.14.4/drivers/gpu/drm/msm/ |
| D | msm_ringbuffer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 static struct dma_fence *msm_job_run(struct drm_sched_job *job) in msm_job_run() argument
16 struct msm_gem_submit *submit = to_msm_submit(job); in msm_job_run()
17 struct msm_fence_context *fctx = submit->ring->fctx; in msm_job_run()
18 struct msm_gpu *gpu = submit->gpu; in msm_job_run()
19 struct msm_drm_private *priv = gpu->dev->dev_private; in msm_job_run()
22 msm_fence_init(submit->hw_fence, fctx); in msm_job_run()
24 mutex_lock(&priv->lru.lock); in msm_job_run()
26 for (i = 0; i < submit->nr_bos; i++) { in msm_job_run()
27 struct drm_gem_object *obj = submit->bos[i].obj; in msm_job_run()
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| /linux-6.14.4/drivers/crypto/caam/ |
| D | jr.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2008-2012 Freescale Semiconductor, Inc.
42 jrpriv->hwrng = !caam_rng_init(dev); in register_algs()
54 if (--active_devs != 0) in unregister_algs()
72 /* Free the resources of crypto-engine */ in caam_jr_crypto_engine_exit()
73 crypto_engine_exit(jrpriv->engine); in caam_jr_crypto_engine_exit()
87 if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS) in caam_jr_stop_processing()
91 clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0); in caam_jr_stop_processing()
94 wr_reg32(&jrp->rregs->jrcommand, jrcr_bits); in caam_jr_stop_processing()
97 while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == in caam_jr_stop_processing()
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| D | intern.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
33 #define JOBR_INTC 0
34 #define JOBR_INTC_TIME_THLD 0
35 #define JOBR_INTC_COUNT_THLD 0
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| /linux-6.14.4/drivers/dma/ |
| D | fsl_raid.h | 13 * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
47 #define FSL_RE_GFM_POLY 0x1d000000
50 #define FSL_RE_CFG1_CBSI 0x08000000
51 #define FSL_RE_CFG1_CBS0 0x00080000
56 #define FSL_RE_PQ_OPCODE 0x1B
57 #define FSL_RE_XOR_OPCODE 0x1A
58 #define FSL_RE_MOVE_OPCODE 0x8
60 #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */
61 #define FSL_RE_CACHEABLE_IO 0x0
62 #define FSL_RE_BUFFER_OUTPUT 0x0
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| /linux-6.14.4/drivers/gpu/drm/xe/ |
| D | xe_exec.c | 1 // SPDX-License-Identifier: MIT
30 * - Passing in a list BO which are read / written to creating implicit syncs
31 * - Binding at exec time
32 * - Flow controlling the ring at exec time
35 * passed into an exec, using the dma-buf implicit sync uAPI, have binds as
36 * separate operations, and using the DRM scheduler to flow control the ring.
60 * Rebinds / dma-resv usage applies to non-compute mode VMs only as for compute
63 * There is no need to flow control the ring in the exec as we write the ring at
64 * submission time and set the DRM scheduler max job limit SIZE_OF_RING /
66 * ring is available.
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