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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
77 * - We have the CDCLK PLL, which generates an output clock based on a
79 * - The CD2X Divider, which divides the output of the PLL based on a
80 * divisor selected from a set of pre-defined choices.
81 * - The CD2X Squasher, which further divides the output based on a
84 * - And, finally, a fixed divider that divides the output frequency by 2.
103 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
104 * - CD2X divider update. Single pipe can be active as the divider update
106 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
107 * - Squash waveform update. Pipes can be active.
[all …]
Dintel_dpll.c1 // SPDX-License-Identifier: MIT
197 * the range value for them is (actual_value - 2).
238 /* LVDS 100mhz refclk limits. */
309 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
310 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
314 * divided-down version of it.
317 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
319 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
320 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
322 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
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/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dpllgt215.c36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
43 lM = max(lM, (int)info->vco1.min_m); in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
45 hM = min(hM, (int)info->vco1.max_m); in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
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/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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/linux-6.14.4/drivers/phy/ti/
Dphy-dm816x-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
46 struct clk *refclk; member
54 otg->host = host; in dm816x_usb_phy_set_host()
56 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
64 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
66 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_peripheral()
76 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
77 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
80 regmap_update_bits(phy->syscon, phy->usb_ctrl, in dm816x_usb_phy_init()
85 regmap_read(phy->syscon, phy->usb_ctrl, &val); in dm816x_usb_phy_init()
[all …]
Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
172 struct clk *refclk; member
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
305 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
307 for (; dpll_map->rate; dpll_map++) { in ti_pipe3_get_dpll_params()
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/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dsmsc,usb3503.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <[email protected]>
15 - smsc,usb3503
16 - smsc,usb3503a
17 - smsc,usb3803
22 connect-gpios:
27 intn-gpios:
[all …]
Docteon-usb.txt7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
Ddcn32_dccg.c34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
43 dccg->ctx->logger
161 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
210 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg32_set_dtbclk_dto()
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <[email protected]>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <[email protected]>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
[all …]
/linux-6.14.4/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
105 /* Refclk selection parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
206 * @refclk: reference clock index
215 unsigned int refclk; member
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/linux-6.14.4/drivers/net/ethernet/arc/
Demac_rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
32 struct clk *refclk; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
[all …]
/linux-6.14.4/drivers/gpu/drm/loongson/
Dlsdc_pixpll.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * refclk: reference frequency, 100 MHz from external oscillator
19 * refclk +-----------+ +------------------+ +---------+ outclk
20 * ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | -------->
21 * | +-----------+ +------------------+ +---------+ ^
27 * +---- bypass (bypass above software configurable clock if set) ----+
29 * outclk = refclk / div_ref * loopc / div_out;
38 * 1) 20 MHz <= refclk / div_ref <= 40Mhz
39 * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
/linux-6.14.4/arch/mips/bcm63xx/
Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
403 return clk->rate; in clk_get_rate()
423 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
424 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
441 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
[all …]
/linux-6.14.4/drivers/gpu/drm/gma500/
Dgma_display.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2006-2011 Intel Corporation
44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
88 struct drm_crtc *crtc, int target, int refclk,
Doaktrail_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk) in mrst_limit() argument
87 struct drm_device *dev = crtc->dev; in mrst_limit()
92 switch (dev_priv->core_freq) { in mrst_limit()
107 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
[all …]
Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
25 int refclk, struct gma_clock_t *best_clock);
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
Ddcn314_dccg.c1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
162 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
171 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
180 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
189 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
204 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
/linux-6.14.4/drivers/net/ethernet/ti/
Dcpts.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
32 #define cpts_read32(c, r) readl_relaxed(&c->reg->r)
33 #define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
37 return (event->high >> PORT_NUMBER_SHIFT) & PORT_NUMBER_MASK; in cpts_event_port()
42 return time_after(jiffies, event->tmo); in event_expired()
47 return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; in event_type()
60 return -1; in cpts_fifo_pop()
69 list_for_each_safe(this, next, &cpts->events) { in cpts_purge_events()
72 list_del_init(&event->list); in cpts_purge_events()
[all …]
/linux-6.14.4/arch/arm/boot/dts/synaptics/
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
/linux-6.14.4/drivers/clk/berlin/
Dbg2.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2.h>
19 #include "berlin2-avpll.h"
20 #include "berlin2-div.h"
21 #include "berlin2-pll.h"
77 * - audio_fast_pll is unknown
78 * - audiohd_pll is unknown
79 * - video0_pll is unknown
[all …]
/linux-6.14.4/drivers/pinctrl/mediatek/
Dpinctrl-mt7620.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
60 FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
63 static struct mtmips_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
79 FUNC("wdt refclk", 0, 17, 1),
83 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
101 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
119 { .compatible = "ralink,mt7620-pinctrl" },
120 { .compatible = "ralink,rt2880-pinmux" },
128 .name = "mt7620-pinctrl",
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dti,am62-audio-refclk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,am62-audio-refclk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jai Luthra <j-[email protected]>
15 - const: ti,am62-audio-refclk
20 "#clock-cells":
27 - compatible
28 - reg
29 - "#clock-cells"
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