| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | mediatek,apmixedsys.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Turquette <[email protected]>
11 - Stephen Boyd <[email protected]>
14 The Mediatek apmixedsys controller provides PLLs to the system.
15 The clock values can be found in <dt-bindings/clock/mt*-clk.h>
16 and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
21 - enum:
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| D | mediatek,mt8195-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-[email protected]>
14 PLLs -->
15 dividers -->
17 -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
27 - enum:
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| D | mediatek,mt8192-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-[email protected]>
19 - enum:
20 - mediatek,mt8192-topckgen
21 - mediatek,mt8192-infracfg
22 - mediatek,mt8192-pericfg
23 - mediatek,mt8192-apmixedsys
[all …]
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| D | mediatek,mt8365-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markus Schneider-Pargmann <[email protected]>
13 The apmixedsys module provides most of PLLs which generated from SoC 26m.
20 - enum:
21 - mediatek,mt8365-topckgen
22 - mediatek,mt8365-infracfg
23 - mediatek,mt8365-apmixedsys
[all …]
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| D | mediatek,mt8188-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Garmin Chang <[email protected]>
14 PLLs -->
15 dividers -->
17 -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
29 - enum:
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| D | mediatek,mt8186-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-[email protected]>
14 PLLs -->
15 dividers -->
17 -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
29 - enum:
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/thermal/ |
| D | mediatek,thermal.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek thermal controller for on-SoC temperatures
10 - Sascha Hauer <[email protected]>
15 controls a mux in the apmixedsys register space via AHB bus accesses, so a
16 phandle to the APMIXEDSYS is also needed.
19 - $ref: thermal-sensor.yaml#
24 - mediatek,mt2701-thermal
25 - mediatek,mt2712-thermal
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| /linux-6.14.4/drivers/clk/mediatek/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
[all …]
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| D | clk-mt6735-apmixedsys.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "clk-mtk.h"
10 #include "clk-pll.h"
12 #include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
87 base = devm_ioremap_resource(&pdev->dev, res); in clk_mt6735_apmixed_probe()
91 clk_data = mtk_devm_alloc_clk_data(&pdev->dev, ARRAY_SIZE(apmixedsys_plls)); in clk_mt6735_apmixed_probe()
93 return -ENOMEM; in clk_mt6735_apmixed_probe()
96 ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls, in clk_mt6735_apmixed_probe()
99 dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret); in clk_mt6735_apmixed_probe()
[all …]
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| D | clk-mt7986-apmixed.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-mux.h"
15 #include "clk-pll.h"
17 #include <dt-bindings/clock/mt7986-clk.h>
62 { .compatible = "mediatek,mt7986-apmixedsys", },
70 struct device_node *node = pdev->dev.of_node; in clk_mt7986_apmixed_probe()
75 return -ENOMEM; in clk_mt7986_apmixed_probe()
[all …]
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| D | clk-mt7981-apmixed.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-mux.h"
17 #include "clk-pll.h"
19 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
64 { .compatible = "mediatek,mt7981-apmixedsys", },
72 struct device_node *node = pdev->dev.of_node; in clk_mt7981_apmixed_probe()
77 return -ENOMEM; in clk_mt7981_apmixed_probe()
[all …]
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| D | clk-mt8516-apmixedsys.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/mt8516-clk.h>
16 #include "clk-mtk.h"
17 #include "clk-pll.h"
78 struct device_node *node = pdev->dev.of_node; in clk_mt8516_apmixed_probe()
79 struct device *dev = &pdev->dev; in clk_mt8516_apmixed_probe()
88 return -ENOMEM; in clk_mt8516_apmixed_probe()
107 { .compatible = "mediatek,mt8516-apmixedsys" },
115 .name = "clk-mt8516-apmixed",
121 MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver");
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| D | clk-mt8135-apmixedsys.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/clock/mt8135-clk.h>
14 #include "clk-mtk.h"
15 #include "clk-pll.h"
53 struct device_node *node = pdev->dev.of_node; in clk_mt8135_apmixed_probe()
58 return -ENOMEM; in clk_mt8135_apmixed_probe()
80 struct device_node *node = pdev->dev.of_node; in clk_mt8135_apmixed_remove()
89 { .compatible = "mediatek,mt8135-apmixedsys" },
98 .name = "clk-mt8135-apmixed",
104 MODULE_DESCRIPTION("MediaTek MT8135 apmixedsys clocks driver");
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| /linux-6.14.4/Documentation/devicetree/bindings/sound/ |
| D | mt8186-afe-pcm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <[email protected]>
14 const: mediatek,mt8186-sound
25 reset-names:
28 mediatek,apmixedsys:
30 description: The phandle of the mediatek apmixedsys controller
42 - description: audio infra sys clock
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| D | mt8192-afe-pcm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <[email protected]>
11 - Shane Chien <[email protected]>
15 const: mediatek,mt8192-audio
23 reset-names:
26 mediatek,apmixedsys:
28 description: The phandle of the mediatek apmixedsys controller
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-decoder.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yunfei Dong <[email protected]>
19 - mediatek,mt8173-vcodec-dec
20 - mediatek,mt8183-vcodec-dec
26 reg-names:
28 - const: misc
29 - const: ld
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
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| /linux-6.14.4/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
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| D | mt8173.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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| D | mt8167.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
32 apmixedsys: apmixedsys@10018000 { label
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| /linux-6.14.4/sound/soc/mediatek/mt8186/ |
| D | mt8186-afe-clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-clk.h"
14 #include "mt8186-audsys-clk.h"
76 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_set_audio_int_bus_parent()
79 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8186_set_audio_int_bus_parent()
80 afe_priv->clk[clk_id]); in mt8186_set_audio_int_bus_parent()
82 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_set_audio_int_bus_parent()
93 struct mt8186_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
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| /linux-6.14.4/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl
9 #include <linux/arm-smccc.h>
14 #include "mt8192-afe-clk.h"
15 #include "mt8192-afe-common.h"
66 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_set_audio_int_bus_parent()
69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
70 afe_priv->clk[clk_id]); in mt8192_set_audio_int_bus_parent()
72 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8192_set_audio_int_bus_parent()
82 struct mt8192_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
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| /linux-6.14.4/arch/arm/boot/dts/mediatek/ |
| D | mt7623.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
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| D | mt8135.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
[all …]
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| /linux-6.14.4/drivers/thermal/mediatek/ |
| D | auxadc_thermal.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
119 #define MT8173_TEMP_MIN -20000
704 * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
719 tmp /= mt->conf->cali_val + mt->o_slope; in raw_to_mcelsius_v1()
720 tmp /= 10000 + mt->adc_ge; in raw_to_mcelsius_v1()
721 tmp *= raw - mt->vts[sensno] - 3350; in raw_to_mcelsius_v1()
724 return mt->degc_cali * 500 - tmp; in raw_to_mcelsius_v1()
740 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); in raw_to_mcelsius_v2()
741 g_oe = mt->adc_oe - 512; in raw_to_mcelsius_v2()
[all …]
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