Home
last modified time | relevance | path

Searched +full:- +full:16 (Results 1 – 25 of 1157) sorted by relevance

12345678910>>...47

/linux-6.14.4/arch/arm64/crypto/
Daes-neon.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-neon.S - AES cipher for ARMv8 NEON
5 * Copyright (C) 2013 - 2017 Linaro Ltd. <[email protected]>
22 /* special case for the neon-bs driver calling into this one for CTS */
45 movi v12.16b, #0x1b
49 ld1 {v16.16b-v19.16b}, [\temp], #64
50 ld1 {v20.16b-v23.16b}, [\temp], #64
51 ld1 {v24.16b-v27.16b}, [\temp], #64
52 ld1 {v28.16b-v31.16b}, [\temp]
71 sub v9.16b, \in\().16b, v15.16b
[all …]
Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
27 .inst 0xce60c800 | (.L\vm << 16) | (.L\vn << 5) | .L\vd
45 * x0: 128-bit key
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
53 ld1 {v1.16b}, [x3];
55 ld1 {v24.16b-v27.16b}, [x4], #64;
[all …]
Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
99 eor RTMP1.16b, s2.16b, s3.16b; \
100 eor RX0.16b, RX0.16b, s1.16b; \
101 eor RX0.16b, RX0.16b, RTMP1.16b; \
103 /* sbox, non-linear part */ \
[all …]
Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <[email protected]>
192 in_bs_ch \b0\().16b, \b1\().16b, \b2\().16b, \b3\().16b, \
193 \b4\().16b, \b5\().16b, \b6\().16b, \b7\().16b
194 inv_gf256 \b6\().16b, \b5\().16b, \b0\().16b, \b3\().16b, \
195 \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
196 \t0\().16b, \t1\().16b, \t2\().16b, \t3\().16b, \
197 \s0\().16b, \s1\().16b, \s2\().16b, \s3\().16b
198 out_bs_ch \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
[all …]
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <[email protected]>
8 /* included by aes-ce.S and aes-neon.S */
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
64 ST5( ld1 {v4.16b}, [x1], #16 )
66 st1 {v0.16b-v3.16b}, [x0], #64
67 ST5( st1 {v4.16b}, [x0], #16 )
73 ld1 {v0.16b}, [x1], #16 /* get next pt block */
75 st1 {v0.16b}, [x0], #16
[all …]
Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
37 * output: r0:r1 (low 128-bits in r0, high in r1)
40 ext T0.16b, m1.16b, m1.16b, #8; \
45 eor T0.16b, T0.16b, T1.16b; \
46 ext T1.16b, RZERO.16b, T0.16b, #8; \
47 ext T0.16b, T0.16b, RZERO.16b, #8; \
48 eor r0.16b, r0.16b, T1.16b; \
[all …]
Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <[email protected]>
61 .arch armv8-a+crypto
80 tbl t3.16b, {\ad\().16b}, perm1.16b // A1
81 tbl t5.16b, {\ad\().16b}, perm2.16b // A2
82 tbl t7.16b, {\ad\().16b}, perm3.16b // A3
96 __pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
109 eor t3.16b, t3.16b, t4.16b // L = E + F
110 eor t5.16b, t5.16b, t6.16b // M = G + H
111 eor t7.16b, t7.16b, t8.16b // N = I + J
[all …]
Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <[email protected]>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
45 // x0 += x1, x3 = rotl32(x3 ^ x0, 16)
47 eor v3.16b, v3.16b, v0.16b
52 eor v4.16b, v1.16b, v2.16b
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
[all …]
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
17 .set .Lv\b\().16b, \b
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
[all …]
Dsm4-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-CCM AEAD Algorithm using ARMv8 Crypto Extensions
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31
35 rev64 vctr.16b, vctr.16b; \
49 ld1 {RMAC.16b}, [x1]
57 ld1 {v0.16b-v3.16b}, [x2], #64
60 eor RMAC.16b, RMAC.16b, v0.16b
62 eor RMAC.16b, RMAC.16b, v1.16b
[all …]
Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <[email protected]>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
14 ld1 {v1.4s}, [x0], #16
18 mov v3.16b, v1.16b
20 0: mov v2.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
[all …]
Dpolyval-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
22 * two-step process only requires 1 finite field reduction for every 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
84 * Later, the 256-bit result can be extracted as:
96 ext v25.16b, X.16b, X.16b, #8
97 ext v26.16b, Y.16b, Y.16b, #8
98 eor v25.16b, v25.16b, X.16b
99 eor v26.16b, v26.16b, Y.16b
[all …]
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd.
15 .arch armv8-a+crypto
20 ld1 {v10.4s-v13.4s}, [\rk]
21 ld1 {v14.4s-v17.4s}, [\tmp], #64
22 ld1 {v18.4s-v21.4s}, [\tmp], #64
23 ld1 {v3.4s-v5.4s}, [\tmp]
27 aese \va\().16b, \vk\().16b
28 aesmc \va\().16b, \va\().16b
[all …]
Dsm4-ce-asm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 ld1 {v24.16b-v27.16b}, [ptr], #64; \
9 ld1 {v28.16b-v31.16b}, [ptr];
21 ext b0.16b, b0.16b, b0.16b, #8; \
22 rev32 b0.16b, b0.16b;
25 rev32 b0.16b, b0.16b; \
47 ext b0.16b, b0.16b, b0.16b, #8; \
48 ext b1.16b, b1.16b, b1.16b, #8; \
49 rev32 b0.16b, b0.16b; \
50 rev32 b1.16b, b1.16b; \
[all …]
Dsm3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
17 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
21 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
29 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
33 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
37 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
41 .inst 0xce408c00 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
54 ext \s4\().16b, \s1\().16b, \s2\().16b, #12
[all …]
/linux-6.14.4/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
19 module_model_id 0x0000 16
23 - e GRBG 0
[all …]
/linux-6.14.4/arch/arm64/lib/
Dcrc-t10dif-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
5 // Copyright (C) 2019-2024 Google LLC
17 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
65 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
72 .arch armv8-a+crypto
96 * Pairwise long polynomial multiplication of two 16-bit values
100 * by two 64-bit values
115 * 2 (w0*x2 ^ w1*x1) << 16 ^ | (y0*z2 ^ y1*z1) << 16 ^
128 * and after performing 8x8->16 bit long polynomial multiplication of
130 * we obtain the following four vectors of 16-bit elements:
[all …]
/linux-6.14.4/arch/arm/mach-rpc/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0
37 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
38 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
39 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
40 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
41 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
42 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
43 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
44 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
45 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
[all …]
/linux-6.14.4/tools/testing/selftests/powerpc/lib/
Dreg.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 #include <ppc-asm.h>
11 /* Non volatile GPR - unsigned long buf[18] */
15 ld 16, 2*8(3)
29 ld 30, 16*8(3)
37 std 16, 2*8(3)
51 std 30, 16*8(3)
56 /* Double Precision Float - double buf[32] */
74 stfd 16, 16*8(3)
93 /* VMX/VSX registers - unsigned long buf[128] */
[all …]
/linux-6.14.4/arch/alpha/kernel/
Dsys_rx164.c1 // SPDX-License-Identifier: GPL-2.0
51 rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); in rx164_enable_irq()
57 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); in rx164_disable_irq()
85 pld &= pld - 1; /* clear least bit set */ in rx164_device_interrupt()
89 handle_irq(16+i); in rx164_device_interrupt()
100 for (i = 16; i < 40; ++i) { in rx164_init_irq()
108 if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL)) in rx164_init_irq()
109 pr_err("Failed to register isa-cascade interrupt\n"); in rx164_init_irq()
123 * 4 10 1 6 11 16
131 * 4 10 5 11 16 6
[all …]
Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
40 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
41 outb(mask >> (16 + ofs * 8), 0x804 + ofs); in cabriolet_update_irq_hw()
47 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
53 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
70 pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16); in cabriolet_device_interrupt()
78 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
82 handle_irq(16 + i); in cabriolet_device_interrupt()
103 for (i = 16; i < 35; ++i) { in common_init_irq()
111 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
[all …]
/linux-6.14.4/drivers/media/platform/ti/omap3isp/
Dnoise_filter_table.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Noise filter table
14 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
15 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
/linux-6.14.4/drivers/video/fbdev/riva/
Dnv_type.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
8 #define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
9 #define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
10 #define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
11 #define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
12 #define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
13 #define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
14 #define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
15 #define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
[all …]
/linux-6.14.4/arch/arm64/kernel/vdso/
Dvgetrandom-chacha.S1 // SPDX-License-Identifier: GPL-2.0
27 * number of blocks of output with nonce 0, taking an input key and 8-bytes
30 * This implementation avoids d8-d15 because they are callee-save in user
39 * x1: 32-byte key input
40 * x2: 8-byte counter input/output
41 * x3: number of 64-byte block to write to output
45 /* copy0 = "expand 32-byte k" */
61 mov state0.16b, copy0.16b
62 mov state1.16b, copy1.16b
63 mov state2.16b, copy2.16b
[all …]
/linux-6.14.4/drivers/scsi/qla2xxx/
Dqla_dbg.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
10 * ----------------------------------------------------------------------
12 * ----------------------------------------------------------------------
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
29 * | | | 0x7073-0x7075 |
[all …]

12345678910>>...47