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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/IR/
D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], [all …]
D	IntrinsicsHexagonDep.td	1 //===----------------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 1063 def int_hexagon_A2_abs : 1066 def int_hexagon_A2_absp : 1069 def int_hexagon_A2_abssat : 1072 def int_hexagon_A2_add : 1075 def int_hexagon_A2_addh_h16_hh : 1078 def int_hexagon_A2_addh_h16_hl : [all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/IR/
D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], [all …]
D	IntrinsicsHexagonDep.td	1 //===----------------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 1063 def int_hexagon_A2_abs : 1066 def int_hexagon_A2_absp : 1069 def int_hexagon_A2_abssat : 1072 def int_hexagon_A2_add : 1075 def int_hexagon_A2_addh_h16_hh : 1078 def int_hexagon_A2_addh_h16_hl : [all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/IR/
D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], [all …]
D	IntrinsicsHexagonDep.td	1 //===----------------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 1063 def int_hexagon_A2_abs : 1066 def int_hexagon_A2_absp : 1069 def int_hexagon_A2_abssat : 1072 def int_hexagon_A2_add : 1075 def int_hexagon_A2_addh_h16_hh : 1078 def int_hexagon_A2_addh_h16_hl : [all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/IR/
D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], [all …]
D	IntrinsicsHexagonDep.td	1 //===----------------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 1063 def int_hexagon_A2_abs : 1066 def int_hexagon_A2_absp : 1069 def int_hexagon_A2_abssat : 1072 def int_hexagon_A2_add : 1075 def int_hexagon_A2_addh_h16_hh : 1078 def int_hexagon_A2_addh_h16_hl : [all …]
/aosp_15_r20/external/llvm/lib/Target/X86/
H A D	X86Schedule.td	`1 //===-- X86Schedule.td - X86 Scheduling Definitions --------- tablegen --===// 8 //===----------------------------------------------------------------------===// 10 // InstrSchedModel annotations for out-of-order CPUs. 17 def ReadAfterLd : SchedRead; 21 def WriteRMW : SchedWrite; 34 // Register-Memory operation. 35 def Ld : SchedWrite; 36 // Register-Register operation. 37 def NAME : X86FoldableSchedWrite { 45 def WriteIMulH : SchedWrite; // Integer multiplication, high part. [all …]`
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/IR/
H A D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], 19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], 24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], [all …]
H A D	IntrinsicsHexagonDep.td	1 //===----------------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 1063 def int_hexagon_A2_abs : 1066 def int_hexagon_A2_absp : 1069 def int_hexagon_A2_abssat : 1072 def int_hexagon_A2_add : 1075 def int_hexagon_A2_addh_h16_hh : 1078 def int_hexagon_A2_addh_h16_hl : [all …]
/aosp_15_r20/external/clang/include/clang/Basic/
H A D	DiagnosticGroups.td	1 //==--- DiagnosticGroups.td - Diagnostic Group Definitions ----------------===// 8 //===----------------------------------------------------------------------===// 10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">; 11 def ImplicitInt : DiagGroup<"implicit-int">; 14 def Implicit : DiagGroup<"implicit", [ 20 def : DiagGroup<"abi">; 21 def AbsoluteValue : DiagGroup<"absolute-value">; 22 def AddressOfTemporary : DiagGroup<"address-of-temporary">; 23 def : DiagGroup<"aggregate-return">; 24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">; [all …]
H A D	DiagnosticSemaKinds.td	1 //==--- DiagnosticSemaKinds.td - libsema diagnostics ----------------------===// 8 //===----------------------------------------------------------------------===// 10 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 17 def note_previous_decl : Note<"%0 declared here">; 18 def note_entity_declared_at : Note<"%0 declared here">; 19 def note_callee_decl : Note<"%0 declared here">; 20 def note_defined_here : Note<"%0 defined here">; 23 def warn_variables_not_in_loop_body : Warning< 27 def warn_redundant_loop_iteration : Warning< [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A D	ARMSchedule.td	1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===// 9 // Instruction scheduling annotations for in-order and out-of-order CPUs. 11 // Here we define the subtarget independent read/write per-operand resources. 17 // Rd <- ADD Rn, Rm, <shift> Rs 18 // Uops \| Latency from register \| Uops - resource requirements - latency 19 // 2 \| Rn: 1 Rm: 4 Rs: 4 \| uop T0, Rm, Rs - P01 - 3 20 // \| \| uopc Rd, Rn, T0 - P01 - 1 [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
H A D	IntrinsicsHexagon.td	1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---- tablegen --===// 4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 //===----------------------------------------------------------------------===// 8 // This file defines all of the Hexagon-specific intrinsics. 10 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 17 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. 24 /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon 71 def int_hexagon_circ_ldd : 76 def int_hexagon_circ_ldw : [all …]
H A D	IntrinsicsAArch64.td	1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines all of the AARCH64-specific intrinsics. 11 //===----------------------------------------------------------------------===// 15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; 16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; 17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; 18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; 20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A D	ARMSchedule.td	1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===// 9 // Instruction scheduling annotations for in-order and out-of-order CPUs. 11 // Here we define the subtarget independent read/write per-operand resources. 17 // Rd <- ADD Rn, Rm, <shift> Rs 18 // Uops \| Latency from register \| Uops - resource requirements - latency 19 // 2 \| Rn: 1 Rm: 4 Rs: 4 \| uop T0, Rm, Rs - P01 - 3 20 // \| \| uopc Rd, Rn, T0 - P01 - 1 [all …]
/aosp_15_r20/external/llvm/lib/Target/ARM/
H A D	ARMSchedule.td	1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------- tablegen --===// 8 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 10 // Instruction scheduling annotations for out-of-order CPUs. 12 // Here we define the subtarget independent read/write per-operand resources. 18 // Rd <- ADD Rn, Rm, <shift> Rs 19 // Uops \| Latency from register \| Uops - resource requirements - latency 20 // 2 \| Rn: 1 Rm: 4 Rs: 4 \| uop T0, Rm, Rs - P01 - 3 21 // \| \| uopc Rd, Rn, T0 - P01 - 1 24 // and one cycle after the result in Rn is available. The micro-ops can execute [all …]
/aosp_15_r20/external/pytorch/torch/_C/
H A D	__init__.pyi.in	2 # mypy: disable-error-code="type-arg" 3 # mypy: allow-untyped-defs 82 def __len__(self, /) -> builtins.int: ... 83 def __getitem__(self, index: builtins.int, /) -> _T_co \| _NestedSequence[_T_co]: ... 84 def __contains__(self, x: builtins.object, /) -> builtins.bool: ... 85 def __iter__(self, /) -> Iterator[_T_co \| _NestedSequence[_T_co]]: ... 86 def __reversed__(self, /) -> Iterator[_T_co \| _NestedSequence[_T_co]]: ... 87 def count(self, value: Any, /) -> builtins.int: ... 88 def index(self, value: Any, /) -> builtins.int: ... 96 def __get__(self, instance, owner=None) -> device: ... [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AVR/
H A D	AVRDevices.td	1 //===---------------------------------------------------------------------===// 3 //===---------------------------------------------------------------------===// 5 // :TODO: Implement the skip errata, see `gcc/config/avr/avr-arch.h` for details 24 // SRAM-relevant instructions. 27 // LD - all 9 variants 28 // ST - all 9 variants 29 // LDD - two variants for Y and Z 30 // STD - two variants for Y and Z 34 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true", 38 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true", [all …]
/aosp_15_r20/external/llvm/lib/Target/Hexagon/
H A D	HexagonIntrinsics.td	1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------- tablegen --===// 8 //===----------------------------------------------------------------------===// 11 // Application-Level Specification 12 // 80-V9418-8 Rev. B 14 //===----------------------------------------------------------------------===// 222 //===----------------------------------------------------------------------===// 225 //===----------------------------------------------------------------------===// 227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>; 228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>; 229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>; [all …]
/aosp_15_r20/external/clang/include/clang/Driver/
H A D	Options.td	1 //===--- Options.td - Options for clang -----------------------------------===// 8 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 20 // DriverOption - The option is a "driver" option, and should not be forwarded 22 def DriverOption : OptionFlag; 24 // LinkerInput - The option is a linker input. 25 def LinkerInput : OptionFlag; 27 // NoArgumentUnused - Don't report argument unused warnings for this option; this 28 // is useful for options like -static or -dynamic which a user may always end up 30 def NoArgumentUnused : OptionFlag; [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A D	AArch64SystemOperands.td	1 //===- AArch64SystemOperands.td ----------------------------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 16 //===----------------------------------------------------------------------===// 18 //===----------------------------------------------------------------------===// 20 def HasCCPP : Predicate<"Subtarget->hasCCPP()">, 23 def HasPAN : Predicate<"Subtarget->hasPAN()">, 25 "ARM v8.1 Privileged Access-Never extension">; 27 def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A D	AVRDevices.td	1 //===---------------------------------------------------------------------===// 3 //===---------------------------------------------------------------------===// 5 // :TODO: Implement the skip errata, see `gcc/config/avr/avr-arch.h` for details 25 // SRAM-relevant instructions. 28 // LD - all 9 variants 29 // ST - all 9 variants 30 // LDD - two variants for Y and Z 31 // STD - two variants for Y and Z 35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true", 39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true", [all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A D	AArch64SchedExynosM4.td	1 //=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --- tablegen --=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 15 // The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16 // in-order stage for decode and dispatch and a wider issue stage. 17 // The execution units and loads and stores are out-of-order. 19 def ExynosM4Model : SchedMachineModel { 33 //===----------------------------------------------------------------------===// [all …]

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