1 /*
2 * Copyright (c) 2012-2018 LK Trusty Authors. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <arch/arch_ops.h>
25 #include <arch/x86.h>
26 #include <dev/interrupt/local_apic.h>
27 #include <dev/interrupt/x86_interrupts.h>
28 #include <err.h>
29 #if WITH_LIB_SM
30 #include <lib/sm.h>
31 #endif
32 #include <kernel/thread.h>
33
34 static spin_lock_t intr_reg_lock;
35 struct int_handler_struct int_handler_table[INT_VECTORS];
36
37 /*
38 * IRQ0 to IRQ7 in Master PIC are tranditionally mapped by the BIOS to
39 * interrupts 8 to 15 (0x08 to 0x0F). However, interrupts from 0x0 to
40 * 0x1f are reseverd for exceptions by Intel x86 architecture. In order
41 * to distinguish exception and external interrupts, it is recommended
42 * to change ths PIC's offset so that IRQs are mapped to un-reserved
43 * interrupts vectors.
44 */
remap_pic(void)45 static void remap_pic(void) {
46 /* Send ICW1 */
47 outp(PIC1, ICW1);
48 outp(PIC2, ICW1);
49
50 /* Send ICW2 to remap */
51 outp(PIC1 + 1, PIC1_BASE_INTR);
52 outp(PIC2 + 1, PIC2_BASE_INTR);
53
54 /* Send ICW3 */
55 outp(PIC1 + 1, ICW3_PIC1);
56 outp(PIC2 + 1, ICW3_PIC2);
57
58 /* Send ICW4 */
59 outp(PIC1 + 1, ICW4);
60 outp(PIC2 + 1, ICW4);
61 }
62
63 /*
64 * PIT is connected to IRQ0 of PIC as hardware timer resource. Trusty Intel
65 * architecture reference utilizes interrupt triggered by PIT as timer
66 * interrupt. To other PIC's IRQs, mask them directly, since Local APIC is
67 * used to handle all other interrupts except timer interrupt.
68 */
mask_all_except_irq0(void)69 static void mask_all_except_irq0(void) {
70 /* Mask all other IRQs except IRQ0(PIT) */
71 outp(PIC1 + 1, 0xfe);
72 outp(PIC2 + 1, 0xff);
73 }
74
75 /*
76 * Mask all IRQs of PIC, since Trusty should not receive any external interrupts
77 * from PIC in Android/Trusty solution.
78 */
mask_all_irqs(void)79 static void mask_all_irqs(void) {
80 /* Mask all other IRQs except IRQ0(PIT) */
81 outp(PIC1 + 1, 0xff);
82 outp(PIC2 + 1, 0xff);
83 }
84
x86_init_interrupts(void)85 void x86_init_interrupts(void) {
86 /* Remap PIC1 IRQ0 to PIC1_BASE_INTR and PIC2 to PIC2_BASE_INTR */
87 remap_pic();
88 mask_all_irqs();
89
90 /* PIC2 interrupts are cascaded through PIC1 and must be unmasked there */
91 unmask_interrupt(PIC2_CASCADE_INTR);
92 }
93
pic_set_mask(unsigned int vector,bool masked)94 static void pic_set_mask(unsigned int vector, bool masked) {
95 uint16_t port;
96 uint line;
97 DEBUG_ASSERT(vector >= PIC1_BASE_INTR);
98 DEBUG_ASSERT(vector < AFTER_PIC_INTR);
99 if (vector < PIC2_BASE_INTR) {
100 port = PIC1 + 1;
101 line = vector - PIC1_BASE_INTR;
102 } else {
103 port = PIC2 + 1;
104 line = vector - PIC2_BASE_INTR;
105 }
106 spin_lock_saved_state_t state;
107 spin_lock_irqsave(&intr_reg_lock, state);
108 uint8_t line_mask = 1U << line;
109 uint8_t current_mask = inp(port);
110 if (masked) {
111 current_mask |= line_mask;
112 } else {
113 current_mask &= ~line_mask;
114 }
115 dprintf(INFO, "new pic mask 0x%x: 0x%x\n", port, current_mask);
116 outp(port, current_mask);
117 spin_unlock_irqrestore(&intr_reg_lock, state);
118 }
119
mask_interrupt(unsigned int vector)120 status_t mask_interrupt(unsigned int vector) {
121 if (vector >= INT_VECTORS) {
122 return ERR_INVALID_ARGS;
123 }
124 if (vector >= PIC1_BASE_INTR && vector < AFTER_PIC_INTR) {
125 pic_set_mask(vector, true);
126 } else {
127 return ERR_NOT_IMPLEMENTED;
128 }
129
130 return NO_ERROR;
131 }
132
platform_mask_irqs(void)133 void platform_mask_irqs(void) {}
134
unmask_interrupt(unsigned int vector)135 status_t unmask_interrupt(unsigned int vector) {
136 if (vector >= INT_VECTORS) {
137 return ERR_INVALID_ARGS;
138 }
139 if (vector >= PIC1_BASE_INTR && vector < AFTER_PIC_INTR) {
140 pic_set_mask(vector, false);
141 } else {
142 return ERR_NOT_IMPLEMENTED;
143 }
144
145 return NO_ERROR;
146 }
147
default_isr(unsigned int vector)148 enum handler_return default_isr(unsigned int vector) {
149 enum handler_return ret = INT_NO_RESCHEDULE;
150
151 #if WITH_LIB_SM
152 /*
153 * Deliver this interrupt to Non-Secure world. At this point,
154 * both Secure and Non-Secure world are all interrupt disabled
155 * after triggering self IPI. This IPI would be acknowledged at
156 * Non-Secure world after world switch.
157 */
158 send_self_ipi(vector);
159 ret = sm_handle_irq();
160 #endif
161
162 lapic_eoi();
163
164 return ret;
165 }
166
platform_irq(x86_iframe_t * frame)167 enum handler_return platform_irq(x86_iframe_t* frame) {
168 /* Get current vector. */
169 unsigned int vector = frame->vector;
170 enum handler_return ret = INT_NO_RESCHEDULE;
171 int_handler handler = NULL;
172 void* arg = NULL;
173 spin_lock_saved_state_t state;
174
175 THREAD_STATS_INC(interrupts);
176
177 spin_lock_irqsave(&intr_reg_lock, state);
178
179 handler = int_handler_table[vector].handler;
180 arg = int_handler_table[vector].arg;
181
182 spin_unlock_irqrestore(&intr_reg_lock, state);
183
184 if (NULL != handler) {
185 ret = handler(arg);
186 if (vector >= PIC1_BASE_INTR && vector < AFTER_PIC_INTR) {
187 if (vector >= PIC2_BASE_INTR) {
188 outp(PIC2, PIC_EOI);
189 }
190 outp(PIC1, PIC_EOI);
191 }
192 } else {
193 ret = default_isr(vector);
194 }
195
196 return ret;
197 }
198
register_int_handler(unsigned int vector,int_handler handler,void * arg)199 void register_int_handler(unsigned int vector, int_handler handler, void* arg) {
200 if (vector >= INT_VECTORS) {
201 panic("register_int_handler: vector out of range %d\n", vector);
202 }
203
204 spin_lock_saved_state_t state;
205 spin_lock_irqsave(&intr_reg_lock, state);
206
207 if (NULL == int_handler_table[vector].handler) {
208 int_handler_table[vector].arg = arg;
209 int_handler_table[vector].handler = handler;
210
211 mb();
212 } else {
213 panic("ISR for vector: %d has been already registered!\n", vector);
214 }
215
216 spin_unlock_irqrestore(&intr_reg_lock, state);
217 }
218
219 #if WITH_LIB_SM
smc_intc_get_next_irq(struct smc32_args * args)220 long smc_intc_get_next_irq(struct smc32_args* args) {
221 long vector;
222
223 for (vector = args->params[0]; vector < INT_VECTORS; vector++) {
224 if (int_handler_table[vector].handler) {
225 return vector;
226 }
227 }
228 return -1;
229 }
230
sm_intc_fiq_enter(void)231 status_t sm_intc_fiq_enter(void) {
232 return NO_ERROR;
233 }
234
sm_intc_enable_interrupts(void)235 enum handler_return sm_intc_enable_interrupts(void) {
236 return INT_NO_RESCHEDULE;
237 }
238 #endif
239