1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef H_ETNA_INTERNAL
25 #define H_ETNA_INTERNAL
26
27 #include <assert.h>
28 #include <stdbool.h>
29 #include <stdint.h>
30
31 #include "hw/common.xml.h"
32 #include "hw/common_3d.xml.h"
33 #include "hw/state.xml.h"
34 #include "hw/state_3d.xml.h"
35
36 #include "drm/etnaviv_drmif.h"
37
38 #define ETNA_NUM_INPUTS (16)
39 #define ETNA_NUM_VARYINGS 16
40 #define ETNA_NUM_LOD (14)
41 #define ETNA_NUM_LAYERS (6)
42 #define ETNA_MAX_UNIFORMS (256)
43 #define ETNA_MAX_CONST_BUF 16
44 #define ETNA_MAX_PIXELPIPES 2
45
46 /* All RS operations must have width%16 = 0 */
47 #define ETNA_RS_WIDTH_MASK (16 - 1)
48 /* RS tiled operations must have height%4 = 0 */
49 #define ETNA_RS_HEIGHT_MASK (3)
50 /* PE render targets must be aligned to 64 bytes */
51 #define ETNA_PE_ALIGNMENT (64)
52
53 /* These demarcate the margin (fixp16) between the computed sizes and the
54 value sent to the chip. These have been set to the numbers used by the
55 Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
56 am not sure whether older hardware was relying on these or they were just a
57 guess. But if so, these need to be moved to the _specs structure.
58 */
59 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
60 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
61 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
62 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
63
64 /* GPU chip 3D specs */
65 struct etna_specs {
66 /* supports SUPERTILE (64x64) tiling? */
67 unsigned can_supertile : 1;
68 /* needs z=(z+w)/2, for older GCxxx */
69 unsigned vs_need_z_div : 1;
70 /* can use VS_RANGE, PS_RANGE registers*/
71 unsigned has_shader_range_registers : 1;
72 /* has the new sin/cos/log functions */
73 unsigned has_new_transcendentals : 1;
74 /* has no limit on the number of constant sources per instruction */
75 unsigned has_no_oneconst_limit : 1;
76 /* has V4_COMPRESSION */
77 unsigned v4_compression : 1;
78 /* supports single-buffer rendering with multiple pixel pipes */
79 unsigned single_buffer : 1;
80 /* has unified uniforms memory */
81 unsigned has_unified_uniforms : 1;
82 /* can load shader instructions from memory */
83 unsigned has_icache : 1;
84 /* ASTC texture support (and has associated states) */
85 unsigned tex_astc : 1;
86 /* has BLT engine instead of RS */
87 unsigned use_blt : 1;
88 /* supports seamless cube map */
89 unsigned seamless_cube_map : 1;
90 /* number of bits per TS tile */
91 unsigned bits_per_tile;
92 /* clear value for TS (dependent on bits_per_tile) */
93 uint32_t ts_clear_value;
94 /* base of vertex texture units */
95 unsigned vertex_sampler_offset;
96 /* number of fragment sampler units */
97 unsigned fragment_sampler_count;
98 /* number of vertex sampler units */
99 unsigned vertex_sampler_count;
100 /* maximum number of vertex element configurations */
101 unsigned vertex_max_elements;
102 /* vertex shader memory address*/
103 uint32_t vs_offset;
104 /* pixel shader memory address*/
105 uint32_t ps_offset;
106 /* vertex shader uniforms address*/
107 uint32_t vs_uniforms_offset;
108 /* pixel shader uniforms address*/
109 uint32_t ps_uniforms_offset;
110 /* vertex/fragment shader max instructions */
111 uint32_t max_instructions;
112 /* maximum number of VS outputs */
113 unsigned max_vs_outputs;
114 /* maximum number of varyings */
115 unsigned max_varyings;
116 /* maximum vertex uniforms */
117 unsigned max_vs_uniforms;
118 /* maximum pixel uniforms */
119 unsigned max_ps_uniforms;
120 /* maximum texture size */
121 unsigned max_texture_size;
122 /* maximum texture size */
123 unsigned max_rendertarget_size;
124 /* available pixel pipes */
125 unsigned pixel_pipes;
126 /* architecture version of NN cores */
127 unsigned nn_core_version;
128 };
129
130 /* Compiled Gallium state. All the different compiled state atoms are woven
131 * together and uploaded only when it is necessary to synchronize the state,
132 * for example before rendering. */
133
134 /* Compiled pipe_blend_color */
135 struct compiled_blend_color {
136 float color[4];
137 uint32_t PE_ALPHA_BLEND_COLOR;
138 uint32_t PE_ALPHA_COLOR_EXT0;
139 uint32_t PE_ALPHA_COLOR_EXT1;
140 };
141
142 /* Compiled pipe_stencil_ref */
143 struct compiled_stencil_ref {
144 uint32_t PE_STENCIL_CONFIG[2];
145 uint32_t PE_STENCIL_CONFIG_EXT[2];
146 };
147
148 /* Compiled pipe_viewport_state */
149 struct compiled_viewport_state {
150 uint32_t PA_VIEWPORT_SCALE_X;
151 uint32_t PA_VIEWPORT_SCALE_Y;
152 uint32_t PA_VIEWPORT_SCALE_Z;
153 uint32_t PA_VIEWPORT_OFFSET_X;
154 uint32_t PA_VIEWPORT_OFFSET_Y;
155 uint32_t PA_VIEWPORT_OFFSET_Z;
156 uint32_t SE_SCISSOR_LEFT;
157 uint32_t SE_SCISSOR_TOP;
158 uint32_t SE_SCISSOR_RIGHT;
159 uint32_t SE_SCISSOR_BOTTOM;
160 uint32_t PE_DEPTH_NEAR;
161 uint32_t PE_DEPTH_FAR;
162 };
163
164 /* Compiled pipe_framebuffer_state */
165 struct compiled_framebuffer_state {
166 uint32_t GL_MULTI_SAMPLE_CONFIG;
167 uint32_t PE_COLOR_FORMAT;
168 uint32_t PE_DEPTH_CONFIG;
169 struct etna_reloc PE_DEPTH_ADDR;
170 struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
171 uint32_t PE_DEPTH_STRIDE;
172 uint32_t PE_HDEPTH_CONTROL;
173 uint32_t PE_DEPTH_NORMALIZE;
174 struct etna_reloc PE_COLOR_ADDR;
175 struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
176 uint32_t PE_COLOR_STRIDE;
177 uint32_t PE_MEM_CONFIG;
178 uint32_t RA_MULTISAMPLE_UNK00E04;
179 uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
180 uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
181 uint32_t TS_MEM_CONFIG;
182 uint32_t TS_DEPTH_CLEAR_VALUE;
183 struct etna_reloc TS_DEPTH_STATUS_BASE;
184 struct etna_reloc TS_DEPTH_SURFACE_BASE;
185 uint32_t TS_COLOR_CLEAR_VALUE;
186 uint32_t TS_COLOR_CLEAR_VALUE_EXT;
187 struct etna_reloc TS_COLOR_STATUS_BASE;
188 struct etna_reloc TS_COLOR_SURFACE_BASE;
189 uint32_t PE_LOGIC_OP;
190 uint32_t PS_CONTROL;
191 uint32_t PS_CONTROL_EXT;
192 bool msaa_mode; /* adds input (and possible temp) to PS */
193 };
194
195 /* Compiled context->create_vertex_elements_state */
196 struct compiled_vertex_elements_state {
197 unsigned num_elements;
198 uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
199 uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
200 uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
201 uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
202 unsigned num_buffers;
203 uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN];
204 uint32_t FE_VERTEX_STREAM_CONTROL[VIVS_NFE_VERTEX_STREAMS__LEN];
205 };
206
207 /* Compiled context->set_vertex_buffer result */
208 struct compiled_set_vertex_buffer {
209 struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
210 };
211
212 /* Compiled linked VS+PS shader state */
213 struct compiled_shader_state {
214 uint32_t RA_CONTROL;
215 uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
216 uint32_t PA_CONFIG;
217 uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
218 uint32_t VS_END_PC;
219 uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
220 uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
221 uint32_t VS_INPUT_COUNT;
222 uint32_t VS_TEMP_REGISTER_CONTROL;
223 uint32_t VS_OUTPUT[8];
224 uint32_t VS_INPUT[4];
225 uint32_t VS_LOAD_BALANCING;
226 uint32_t VS_START_PC;
227 uint32_t PS_END_PC;
228 uint32_t PS_OUTPUT_REG;
229 uint32_t PS_INPUT_COUNT;
230 uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
231 uint32_t PS_TEMP_REGISTER_CONTROL;
232 uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
233 uint32_t PS_START_PC;
234 uint32_t GL_VARYING_TOTAL_COMPONENTS;
235 uint32_t GL_VARYING_NUM_COMPONENTS[2];
236 uint32_t GL_VARYING_COMPONENT_USE[2];
237 uint32_t GL_HALTI5_SH_SPECIALS;
238 uint32_t FE_HALTI5_ID_CONFIG;
239 unsigned vs_inst_mem_size;
240 unsigned ps_inst_mem_size;
241 uint32_t *VS_INST_MEM;
242 uint32_t *PS_INST_MEM;
243 struct etna_reloc PS_INST_ADDR;
244 struct etna_reloc VS_INST_ADDR;
245 unsigned writes_z:1;
246 unsigned uses_discard:1;
247 };
248
249 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
250 * field_size must be a power of two, and <= 32. */
251 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
252 uint32_t name[(num) * (field_size) / 32]
253
254 static inline void
etna_bitarray_set(uint32_t * array,size_t array_size,size_t field_size,size_t index,uint32_t value)255 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
256 size_t index, uint32_t value)
257 {
258 size_t shift = (index * field_size) % 32;
259 size_t offset = (index * field_size) / 32;
260
261 assert(index < array_size * 32 / field_size);
262 assert(value < 1 << field_size);
263
264 array[offset] |= value << shift;
265 }
266
267 #define etna_bitarray_set(array, field_size, index, value) \
268 etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
269
270 #endif
271