1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ 4 #define __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ 5 6 #include <acpi/acpi_device.h> 7 8 #define RP_MUTEX_NAME "RPMX" 9 10 enum acpi_pcie_rp_pm_emit { 11 ACPI_PCIE_RP_EMIT_NONE = 0x00, /* None */ 12 ACPI_PCIE_RP_EMIT_L23 = 0x01, /* L23 */ 13 ACPI_PCIE_RP_EMIT_PSD0 = 0x02, /* PSD0 */ 14 ACPI_PCIE_RP_EMIT_SRCK = 0x04, /* SRCK */ 15 ACPI_PCIE_RP_EMIT_L23_PSD0 = 0x03, /* L23, PSD0 */ 16 ACPI_PCIE_RP_EMIT_L23_SRCK = 0x05, /* L23, SRCK */ 17 ACPI_PCIE_RP_EMIT_PSD0_SRCK = 0x06, /* PSD0, SRCK */ 18 ACPI_PCIE_RP_EMIT_ALL = 0x07 /* L23, PSD0, SRCK */ 19 }; 20 21 /* Device support at least one of enable/reset GPIO. */ 22 struct soc_intel_common_block_pcie_rtd3_config { 23 const char *desc; 24 25 /* GPIO used to enable device. */ 26 struct acpi_gpio enable_gpio; 27 /* Delay to be inserted after device is enabled. */ 28 unsigned int enable_delay_ms; 29 /* Delay to be inserted after device is disabled. */ 30 unsigned int enable_off_delay_ms; 31 32 /* GPIO used to take device out of reset or to put it into reset. */ 33 struct acpi_gpio reset_gpio; 34 /* Delay to be inserted after device is taken out of reset. */ 35 unsigned int reset_delay_ms; 36 /* Delay to be inserted after device is put into reset. */ 37 unsigned int reset_off_delay_ms; 38 39 /* 40 * SRCCLK assigned to this root port which will be turned off via PMC IPC. 41 * If set to -1 then the clock will not be disabled in D3. 42 */ 43 int srcclk_pin; 44 45 /* When set to true, this will add a _DSD which contains a single 46 property, `DmaProperty`, set to 1, under the ACPI Device. */ 47 bool add_acpi_dma_property; 48 49 /* 50 * Add device property indicating the device provides an external PCI port 51 * for the OS to apply security restrictions. 52 */ 53 bool add_acpi_external_facing_port; 54 55 /* 56 * Allow a device to add the RuntimeD3Storage property even if the detected 57 * PCI device does not identify as storage class. 58 */ 59 bool is_storage; 60 61 /* 62 * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. 63 */ 64 bool disable_l23; 65 66 /* 67 * Provides L23, modPHY gating, source clock enabling methods to the device 68 * connected root port, mainly used in the device ACPI methods such as reset. 69 * The methods to export are following this table: 70 *-----------------------------------------------------------------------------------* 71 | ext_pm_support | disable_l123 | srcclk_pin | rp_type | exported methods | 72 *----------------+--------------+------------+-------------+------------------------* 73 | false | - | - | - | None | 74 | true | true | =0 | PCIE_RP_CPU | None | 75 | true | true | =0 | PCIE_RP_PCH | SRCK | 76 | true | true | >0 | PCIE_RP_CPU | PSD0 | 77 | true | true | >0 | PCIE_RP_PCH | PSD0, SRCK | 78 | true | false | =0 | PCIE_RP_CPU | L23D, LD23 | 79 | true | false | =0 | PCIE_RP_PCH | L23D, LD23, SRCK | 80 | true | false | >0 | PCIE_RP_CPU | L23D, LD23, PSD0 | 81 | true | false | >0 | PCIE_RP_PCH | L23D, LD23, PSD0, SRCK | 82 *-----------------------------------------------------------------------------------* 83 */ 84 enum acpi_pcie_rp_pm_emit ext_pm_support; 85 86 /* 87 * Add support to skip _OFF and _ON execution when needed, such as reloading 88 * the device driver. 89 */ 90 bool skip_on_off_support; 91 92 /* 93 * Indicates the root port mutex is used for _ON and _OFF, the companion device driver 94 * such as WWAN driver should also acquire this mutex in methods that access the same HW 95 * resource, such as PERST# GPIO pin. 96 */ 97 bool use_rp_mutex; 98 }; 99 100 #endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ 101