1 /* 2 * Copyright © 2023 Valve Corporation 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef RADV_NIR_H 8 #define RADV_NIR_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include "amd_family.h" 13 #include "nir.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 typedef struct nir_shader nir_shader; 20 struct radeon_info; 21 struct radv_pipeline_layout; 22 struct radv_shader_stage; 23 struct radv_shader_info; 24 struct radv_shader_args; 25 struct radv_shader_layout; 26 struct radv_device; 27 struct radv_graphics_state_key; 28 29 void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, 30 const struct radv_shader_stage *stage); 31 32 void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage, 33 const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi); 34 35 bool radv_nir_lower_hit_attrib_derefs(nir_shader *shader); 36 37 bool radv_nir_lower_ray_payload_derefs(nir_shader *shader, uint32_t offset); 38 39 bool radv_nir_lower_ray_queries(nir_shader *shader, struct radv_device *device); 40 41 bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_shader_stage *vs_stage, 42 const struct radv_graphics_state_key *gfx_state, const struct radeon_info *gpu_info); 43 44 bool radv_nir_lower_primitive_shading_rate(nir_shader *nir, enum amd_gfx_level gfx_level); 45 46 bool radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stage *fs_stage, 47 const struct radv_graphics_state_key *gfx_state); 48 49 bool radv_nir_lower_fs_barycentric(nir_shader *shader, const struct radv_graphics_state_key *gfx_state, 50 unsigned rast_prim); 51 52 bool radv_nir_lower_intrinsics_early(nir_shader *nir, bool lower_view_index_to_zero); 53 54 bool radv_nir_lower_view_index(nir_shader *nir); 55 56 bool radv_nir_lower_viewport_to_zero(nir_shader *nir); 57 58 bool radv_nir_export_multiview(nir_shader *nir); 59 60 void radv_nir_lower_io_to_scalar_early(nir_shader *nir, nir_variable_mode mask); 61 62 unsigned radv_map_io_driver_location(unsigned semantic); 63 64 void radv_nir_lower_io(struct radv_device *device, nir_shader *nir); 65 66 bool radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *stage); 67 68 void radv_nir_lower_poly_line_smooth(nir_shader *nir, const struct radv_graphics_state_key *gfx_state); 69 70 bool radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size); 71 72 bool radv_nir_lower_draw_id_to_zero(nir_shader *shader); 73 74 bool radv_nir_remap_color_attachment(nir_shader *shader, const struct radv_graphics_state_key *gfx_state); 75 76 typedef struct radv_nir_opt_tid_function_options { 77 bool use_masked_swizzle_amd : 1; 78 bool use_dpp16_shift_amd : 1; 79 bool use_shuffle_xor : 1; 80 bool use_clustered_rotate : 1; 81 /* The can be smaller than the api subgroup/ballot size 82 * if some invocations are always inactive. 83 */ 84 uint8_t hw_subgroup_size; 85 uint8_t hw_ballot_bit_size; 86 uint8_t hw_ballot_num_comp; 87 } radv_nir_opt_tid_function_options; 88 89 bool radv_nir_opt_tid_function(nir_shader *shader, const radv_nir_opt_tid_function_options *options); 90 91 #ifdef __cplusplus 92 } 93 #endif 94 95 #endif /* RADV_NIR_H */ 96