1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Register map for Exynos5 PMU */ 4 5 #ifndef CPU_SAMSUNG_EXYNOS5420_POWER_H 6 #define CPU_SAMSUNG_EXYNOS5420_POWER_H 7 8 #include <soc/cpu.h> 9 10 /* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */ 11 void power_enable_hw_thermal_trip(void); 12 13 #define MIPI_PHY1_CONTROL_ENABLE (1 << 0) 14 #define MIPI_PHY1_CONTROL_M_RESETN (1 << 2) 15 16 #define POWER_USB_PHY_CTRL_EN (1 << 0) 17 #define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) 18 #define POWER_ENABLE_HW_TRIP (1UL << 31) 19 20 #define EXYNOS_DP_PHY_ENABLE (1 << 0) 21 22 /* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ 23 #define PMU_DEBUG_XXTI 0x1000 24 /* Mask bit[12:8] for xxti clock selection */ 25 #define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 26 27 /* Power Management Unit register map */ 28 struct exynos5_power { 29 /* Add registers as and when required */ 30 uint32_t om_stat; /* 0x0000 */ 31 uint8_t reserved1[0x03fc]; 32 uint32_t sw_reset; /* 0x0400 */ 33 uint8_t reserved2[0x0300]; 34 uint32_t usb_drd0_phy_ctrl; /* 0x0704 */ 35 uint32_t usb_drd1_phy_ctrl; /* 0x0708 */ 36 uint32_t usb_host_phy_ctrl; /* 0x070c */ 37 uint8_t reserved3[0x4]; 38 uint32_t mipi_phy1_control; /* 0x0714 */ 39 uint8_t reserved4[0x8]; 40 uint32_t dptx_phy_control; /* 0x0720 */ 41 uint8_t reserved5[0xdc]; 42 uint32_t inform0; /* 0x0800 */ 43 uint32_t inform1; /* 0x0804 */ 44 uint8_t reserved6[0x0f8]; 45 uint32_t spare0; /* 0x0900 */ 46 uint8_t reserved7[0x0fc]; 47 uint32_t pmu_debug; /* 0x0a00 */ 48 uint8_t reserved8[0x15fc]; 49 struct { /* 0x2000 */ 50 uint32_t config; /* 0x00 */ 51 uint32_t status; /* 0x04 */ 52 uint8_t reserved[0x78]; 53 } arm_core[4]; 54 uint8_t reserved9[0xe04]; 55 uint32_t padret_dram_status; /* 0x3004 */ 56 uint8_t reservedA[0xe0]; 57 uint32_t padret_uart_opt; /* 0x30e8 */ 58 uint8_t reservedB[0xfc]; 59 uint32_t padret_dram_cblk_opt; /* 0x31e8 */ 60 uint8_t reservedC[0x120]; 61 uint32_t ps_hold_ctrl; /* 0x330c */ 62 } __packed; 63 check_member(exynos5_power, ps_hold_ctrl, 0x330c); 64 65 static struct exynos5_power *const exynos_power = (void *)EXYNOS5_POWER_BASE; 66 67 /** 68 * Perform a software reset. 69 */ 70 void power_reset(void); 71 72 /** 73 * Power off the system; it should never return. 74 */ 75 void power_shutdown(void); 76 77 /* Enable DPTX PHY */ 78 void power_enable_dp_phy(void); 79 80 /* Initialize the pmic voltages to power up the system */ 81 int power_init(void); 82 83 /* Read the reset status. */ 84 uint32_t power_read_reset_status(void); 85 86 /* Read the resume function and call it. */ 87 void power_exit_wakeup(void); 88 89 /* pmu debug is used for xclkout, enable xclkout with source as XXTI */ 90 void power_enable_xclkout(void); 91 92 /* Release UART retention on resume (only for debugging, may conflict with 93 * kernel). */ 94 void power_release_uart_retention(void); 95 96 #endif 97