1 /**
2 * \file
3 *
4 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
5 *
6 * \asf_license_start
7 *
8 * \page License
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 *
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 *
20 * 3. The name of Atmel may not be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * 4. This software may only be redistributed and used in connection with an
24 * Atmel microcontroller product.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 * \asf_license_stop
39 *
40 */
41 /*
42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
43 */
44
45 #include "samv71.h"
46
47 /* @cond 0 */
48 /**INDENT-OFF**/
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 /**INDENT-ON**/
53 /* @endcond */
54
55 /* %ATMEL_SYSTEM% */
56 /* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */
57 /* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */
58 #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
59 #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x31U) | \
60 CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
61 #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | (1<<8))
62
63 uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
64
65 /**
66 * \brief Setup the microcontroller system.
67 * Initialize the System and update the SystemFrequency variable.
68 */
SystemInit(void)69 void SystemInit( void )
70 {
71 /* Set FWS according to SYS_BOARD_MCKR configuration */
72 EFC->EEFC_FMR = EEFC_FMR_FWS(5);
73
74 /* Initialize main oscillator */
75 if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
76 {
77 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
78
79 while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) )
80 {
81 }
82 }
83
84 /* Switch to 3-20MHz Xtal oscillator */
85 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
86
87 while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) )
88 {
89 }
90
91 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
92
93 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
94 {
95 }
96
97 /* Initialize PLLA */
98 PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
99 while ( !(PMC->PMC_SR & PMC_SR_LOCKA) )
100 {
101 }
102
103 /* Switch to main clock */
104 PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
105 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
106 {
107 }
108
109 /* Switch to PLLA */
110 PMC->PMC_MCKR = SYS_BOARD_MCKR;
111 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
112 {
113 }
114
115 SystemCoreClock = CHIP_FREQ_CPU_MAX;
116 }
117
SystemCoreClockUpdate(void)118 void SystemCoreClockUpdate( void )
119 {
120 /* Determine clock frequency according to clock register values */
121 switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
122 {
123 case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
124 if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
125 {
126 SystemCoreClock = CHIP_FREQ_XTAL_32K;
127 }
128 else
129 {
130 SystemCoreClock = CHIP_FREQ_SLCK_RC;
131 }
132 break;
133
134 case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
135 if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
136 {
137 SystemCoreClock = CHIP_FREQ_XTAL_12M;
138 }
139 else
140 {
141 SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
142
143 switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
144 {
145 case CKGR_MOR_MOSCRCF_4_MHz:
146 break;
147
148 case CKGR_MOR_MOSCRCF_8_MHz:
149 SystemCoreClock *= 2U;
150 break;
151
152 case CKGR_MOR_MOSCRCF_12_MHz:
153 SystemCoreClock *= 3U;
154 break;
155
156 default:
157 break;
158 }
159 }
160 break;
161
162 case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
163 if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
164 {
165 SystemCoreClock = CHIP_FREQ_XTAL_12M ;
166 }
167 else
168 {
169 SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
170
171 switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
172 {
173 case CKGR_MOR_MOSCRCF_4_MHz:
174 break;
175
176 case CKGR_MOR_MOSCRCF_8_MHz:
177 SystemCoreClock *= 2U;
178 break;
179
180 case CKGR_MOR_MOSCRCF_12_MHz:
181 SystemCoreClock *= 3U;
182 break;
183
184 default:
185 break;
186 }
187 }
188
189 if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK )
190 {
191 SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U);
192 SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos));
193 }
194 break;
195
196 default:
197 break;
198 }
199
200 if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
201 {
202 SystemCoreClock /= 3U;
203 }
204 else
205 {
206 SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
207 }
208 }
209 /**
210 * Initialize flash.
211 */
system_init_flash(uint32_t ul_clk)212 void system_init_flash( uint32_t ul_clk )
213 {
214 /* Set FWS for embedded Flash access according to operating frequency */
215 if ( ul_clk < CHIP_FREQ_FWS_0 )
216 {
217 EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
218 }
219 else
220 {
221 if (ul_clk < CHIP_FREQ_FWS_1)
222 {
223 EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
224 }
225 else
226 {
227 if (ul_clk < CHIP_FREQ_FWS_2)
228 {
229 EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
230 }
231 else
232 {
233 if ( ul_clk < CHIP_FREQ_FWS_3 )
234 {
235 EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
236 }
237 else
238 {
239 if ( ul_clk < CHIP_FREQ_FWS_4 )
240 {
241 EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
242 }
243 else
244 {
245 EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
246 }
247 }
248 }
249 }
250 }
251 }
252 /* @cond 0 */
253 /**INDENT-OFF**/
254 #ifdef __cplusplus
255 }
256 #endif
257 /**INDENT-ON**/
258 /* @endcond */
259