1 /**
2 * \file
3 *
4 * \brief Uart Serial for SAM.
5 *
6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43 /*
44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45 */
46 #ifndef _UART_SERIAL_H_
47 #define _UART_SERIAL_H_
48
49 #include "compiler.h"
50 #include "sysclk.h"
51 #if (SAMG55)
52 #include "flexcom.h"
53 #endif
54 #if ((!SAM4L) && (!SAMG55))
55 #include "uart.h"
56 #endif
57 #include "usart.h"
58
59 /**
60 * \name Serial Management Configuration
61 */
62 //! @{
63 #include "conf_uart_serial.h"
64
65 //! @}
66
67 /** Input parameters when initializing RS232 and similar modes. */
68 typedef struct uart_rs232_options {
69 /** Set baud rate of the USART (unused in slave modes). */
70 uint32_t baudrate;
71
72 /** Number of bits to transmit as a character (5 to 9). */
73 uint32_t charlength;
74
75 /**
76 * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc,
77 * USART_PMODE_ODD_gc.
78 */
79 uint32_t paritytype;
80
81 /**
82 * Number of stop bits between two characters:
83 * true: 2 stop bits
84 * false: 1 stop bit
85 */
86 bool stopbits;
87
88 } usart_rs232_options_t;
89
90 typedef usart_rs232_options_t usart_serial_options_t;
91
92 typedef Usart *usart_if;
93
94 /**
95 * \brief Initializes the Usart in master mode.
96 *
97 * \param p_usart Base address of the USART instance.
98 * \param opt Options needed to set up RS232 communication (see
99 * \ref usart_options_t).
100 */
usart_serial_init(usart_if p_usart,usart_serial_options_t * opt)101 static inline void usart_serial_init(usart_if p_usart,
102 usart_serial_options_t *opt)
103 {
104 #if ((!SAM4L) && (!SAMG55))
105 sam_uart_opt_t uart_settings;
106 uart_settings.ul_mck = sysclk_get_peripheral_hz();
107 uart_settings.ul_baudrate = opt->baudrate;
108 uart_settings.ul_mode = opt->paritytype;
109 #endif
110
111 sam_usart_opt_t usart_settings;
112 usart_settings.baudrate = opt->baudrate;
113 usart_settings.char_length = opt->charlength;
114 usart_settings.parity_type = opt->paritytype;
115 usart_settings.stop_bits= opt->stopbits;
116 usart_settings.channel_mode= US_MR_CHMODE_NORMAL;
117
118 #ifdef UART
119 if (UART == (Uart*)p_usart) {
120 sysclk_enable_peripheral_clock(ID_UART);
121 /* Configure UART */
122 uart_init((Uart*)p_usart, &uart_settings);
123 }
124 #else
125 # ifdef UART0
126 if (UART0 == (Uart*)p_usart) {
127 sysclk_enable_peripheral_clock(ID_UART0);
128 /* Configure UART */
129 uart_init((Uart*)p_usart, &uart_settings);
130 }
131 # endif
132 # ifdef UART1
133 if (UART1 == (Uart*)p_usart) {
134 sysclk_enable_peripheral_clock(ID_UART1);
135 /* Configure UART */
136 uart_init((Uart*)p_usart, &uart_settings);
137 }
138 # endif
139 # ifdef UART2
140 if (UART2 == (Uart*)p_usart) {
141 sysclk_enable_peripheral_clock(ID_UART2);
142 /* Configure UART */
143 uart_init((Uart*)p_usart, &uart_settings);
144 }
145 # endif
146 # ifdef UART3
147 if (UART3 == (Uart*)p_usart) {
148 sysclk_enable_peripheral_clock(ID_UART3);
149 /* Configure UART */
150 uart_init((Uart*)p_usart, &uart_settings);
151 }
152 # endif
153 #endif /* ifdef UART */
154
155
156 #ifdef USART
157 if (USART == p_usart) {
158 #if (!SAM4L)
159 sysclk_enable_peripheral_clock(ID_USART);
160 /* Configure USART */
161 usart_init_rs232(p_usart, &usart_settings,
162 sysclk_get_peripheral_hz());
163 #endif
164 #if (SAM4L)
165 sysclk_enable_peripheral_clock(p_usart);
166 /* Configure USART */
167 usart_init_rs232(p_usart, &usart_settings,
168 sysclk_get_peripheral_bus_hz(p_usart));
169 #endif
170 /* Enable the receiver and transmitter. */
171 usart_enable_tx(p_usart);
172 usart_enable_rx(p_usart);
173 }
174 #else
175 # ifdef USART0
176 if (USART0 == p_usart) {
177 #if (!SAM4L)
178 #if (SAMG55)
179 flexcom_enable(FLEXCOM0);
180 flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART);
181 #else
182 sysclk_enable_peripheral_clock(ID_USART0);
183 #endif
184 /* Configure USART */
185 usart_init_rs232(p_usart, &usart_settings,
186 sysclk_get_peripheral_hz());
187 #endif
188 #if (SAM4L)
189 sysclk_enable_peripheral_clock(p_usart);
190 /* Configure USART */
191 usart_init_rs232(p_usart, &usart_settings,
192 sysclk_get_peripheral_bus_hz(p_usart));
193 #endif
194 /* Enable the receiver and transmitter. */
195 usart_enable_tx(p_usart);
196 usart_enable_rx(p_usart);
197 }
198 # endif
199 # ifdef USART1
200 if (USART1 == p_usart) {
201 #if (!SAM4L)
202 #if (SAMG55)
203 flexcom_enable(FLEXCOM1);
204 flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART);
205 #else
206 sysclk_enable_peripheral_clock(ID_USART1);
207 #endif
208 /* Configure USART */
209 usart_init_rs232(p_usart, &usart_settings,
210 sysclk_get_peripheral_hz());
211 #endif
212 #if (SAM4L)
213 sysclk_enable_peripheral_clock(p_usart);
214 /* Configure USART */
215 usart_init_rs232(p_usart, &usart_settings,
216 sysclk_get_peripheral_bus_hz(p_usart));
217 #endif
218 /* Enable the receiver and transmitter. */
219 usart_enable_tx(p_usart);
220 usart_enable_rx(p_usart);
221 }
222 # endif
223 # ifdef USART2
224 if (USART2 == p_usart) {
225 #if (!SAM4L)
226 #if (SAMG55)
227 flexcom_enable(FLEXCOM2);
228 flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART);
229 #else
230 sysclk_enable_peripheral_clock(ID_USART2);
231 #endif
232 /* Configure USART */
233 usart_init_rs232(p_usart, &usart_settings,
234 sysclk_get_peripheral_hz());
235 #endif
236 #if (SAM4L)
237 sysclk_enable_peripheral_clock(p_usart);
238 /* Configure USART */
239 usart_init_rs232(p_usart, &usart_settings,
240 sysclk_get_peripheral_bus_hz(p_usart));
241 #endif
242 /* Enable the receiver and transmitter. */
243 usart_enable_tx(p_usart);
244 usart_enable_rx(p_usart);
245 }
246 # endif
247 # ifdef USART3
248 if (USART3 == p_usart) {
249 #if (!SAM4L)
250 #if (SAMG55)
251 flexcom_enable(FLEXCOM3);
252 flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART);
253 #else
254 sysclk_enable_peripheral_clock(ID_USART3);
255 #endif
256 /* Configure USART */
257 usart_init_rs232(p_usart, &usart_settings,
258 sysclk_get_peripheral_hz());
259 #endif
260 #if (SAM4L)
261 sysclk_enable_peripheral_clock(p_usart);
262 /* Configure USART */
263 usart_init_rs232(p_usart, &usart_settings,
264 sysclk_get_peripheral_bus_hz(p_usart));
265 #endif
266 /* Enable the receiver and transmitter. */
267 usart_enable_tx(p_usart);
268 usart_enable_rx(p_usart);
269 }
270 # endif
271 # ifdef USART4
272 if (USART4 == p_usart) {
273 #if (!SAM4L)
274 #if (SAMG55)
275 flexcom_enable(FLEXCOM4);
276 flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART);
277 #else
278 sysclk_enable_peripheral_clock(ID_USART4);
279 #endif
280 /* Configure USART */
281 usart_init_rs232(p_usart, &usart_settings,
282 sysclk_get_peripheral_hz());
283 #endif
284 #if (SAM4L)
285 sysclk_enable_peripheral_clock(p_usart);
286 /* Configure USART */
287 usart_init_rs232(p_usart, &usart_settings,
288 sysclk_get_peripheral_bus_hz(p_usart));
289 #endif
290 /* Enable the receiver and transmitter. */
291 usart_enable_tx(p_usart);
292 usart_enable_rx(p_usart);
293 }
294 # endif
295 # ifdef USART5
296 if (USART5 == p_usart) {
297 #if (!SAM4L)
298 #if (SAMG55)
299 flexcom_enable(FLEXCOM5);
300 flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART);
301 #else
302 sysclk_enable_peripheral_clock(ID_USART5);
303 #endif
304 /* Configure USART */
305 usart_init_rs232(p_usart, &usart_settings,
306 sysclk_get_peripheral_hz());
307 #endif
308 #if (SAM4L)
309 sysclk_enable_peripheral_clock(p_usart);
310 /* Configure USART */
311 usart_init_rs232(p_usart, &usart_settings,
312 sysclk_get_peripheral_bus_hz(p_usart));
313 #endif
314 /* Enable the receiver and transmitter. */
315 usart_enable_tx(p_usart);
316 usart_enable_rx(p_usart);
317 }
318 # endif
319 # ifdef USART6
320 if (USART6 == p_usart) {
321 #if (!SAM4L)
322 #if (SAMG55)
323 flexcom_enable(FLEXCOM6);
324 flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART);
325 #else
326 sysclk_enable_peripheral_clock(ID_USART6);
327 #endif
328 /* Configure USART */
329 usart_init_rs232(p_usart, &usart_settings,
330 sysclk_get_peripheral_hz());
331 #endif
332 #if (SAM4L)
333 sysclk_enable_peripheral_clock(p_usart);
334 /* Configure USART */
335 usart_init_rs232(p_usart, &usart_settings,
336 sysclk_get_peripheral_bus_hz(p_usart));
337 #endif
338 /* Enable the receiver and transmitter. */
339 usart_enable_tx(p_usart);
340 usart_enable_rx(p_usart);
341 }
342 # endif
343 # ifdef USART7
344 if (USART7 == p_usart) {
345 #if (!SAM4L)
346 #if (SAMG55)
347 flexcom_enable(FLEXCOM7);
348 flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART);
349 #else
350 sysclk_enable_peripheral_clock(ID_USART7);
351 #endif
352 /* Configure USART */
353 usart_init_rs232(p_usart, &usart_settings,
354 sysclk_get_peripheral_hz());
355 #endif
356 #if (SAM4L)
357 sysclk_enable_peripheral_clock(p_usart);
358 /* Configure USART */
359 usart_init_rs232(p_usart, &usart_settings,
360 sysclk_get_peripheral_bus_hz(p_usart));
361 #endif
362 /* Enable the receiver and transmitter. */
363 usart_enable_tx(p_usart);
364 usart_enable_rx(p_usart);
365 }
366 # endif
367
368 #endif /* ifdef USART */
369
370 }
371
372 /**
373 * \brief Sends a character with the USART.
374 *
375 * \param p_usart Base address of the USART instance.
376 * \param c Character to write.
377 *
378 * \return Status.
379 * \retval 1 The character was written.
380 * \retval 0 The function timed out before the USART transmitter became
381 * ready to send.
382 */
usart_serial_putchar(usart_if p_usart,const uint8_t c)383 static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c)
384 {
385 #ifdef UART
386 if (UART == (Uart*)p_usart) {
387 while (uart_write((Uart*)p_usart, c)!=0);
388 return 1;
389 }
390 #else
391 # ifdef UART0
392 if (UART0 == (Uart*)p_usart) {
393 while (uart_write((Uart*)p_usart, c)!=0);
394 return 1;
395 }
396 # endif
397 # ifdef UART1
398 if (UART1 == (Uart*)p_usart) {
399 while (uart_write((Uart*)p_usart, c)!=0);
400 return 1;
401 }
402 # endif
403 # ifdef UART2
404 if (UART2 == (Uart*)p_usart) {
405 while (uart_write((Uart*)p_usart, c)!=0);
406 return 1;
407 }
408 # endif
409 # ifdef UART3
410 if (UART3 == (Uart*)p_usart) {
411 while (uart_write((Uart*)p_usart, c)!=0);
412 return 1;
413 }
414 # endif
415 #endif /* ifdef UART */
416
417
418 #ifdef USART
419 if (USART == p_usart) {
420 while (usart_write(p_usart, c)!=0);
421 return 1;
422 }
423 #else
424 # ifdef USART0
425 if (USART0 == p_usart) {
426 while (usart_write(p_usart, c)!=0);
427 return 1;
428 }
429 # endif
430 # ifdef USART1
431 if (USART1 == p_usart) {
432 while (usart_write(p_usart, c)!=0);
433 return 1;
434 }
435 # endif
436 # ifdef USART2
437 if (USART2 == p_usart) {
438 while (usart_write(p_usart, c)!=0);
439 return 1;
440 }
441 # endif
442 # ifdef USART3
443 if (USART3 == p_usart) {
444 while (usart_write(p_usart, c)!=0);
445 return 1;
446 }
447 # endif
448 # ifdef USART4
449 if (USART4 == p_usart) {
450 while (usart_write(p_usart, c)!=0);
451 return 1;
452 }
453 # endif
454 # ifdef USART5
455 if (USART5 == p_usart) {
456 while (usart_write(p_usart, c)!=0);
457 return 1;
458 }
459 # endif
460 # ifdef USART6
461 if (USART6 == p_usart) {
462 while (usart_write(p_usart, c)!=0);
463 return 1;
464 }
465 # endif
466 # ifdef USART7
467 if (USART7 == p_usart) {
468 while (usart_write(p_usart, c)!=0);
469 return 1;
470 }
471 # endif
472 #endif /* ifdef USART */
473
474 return 0;
475 }
476 /**
477 * \brief Waits until a character is received, and returns it.
478 *
479 * \param p_usart Base address of the USART instance.
480 * \param data Data to read
481 *
482 */
usart_serial_getchar(usart_if p_usart,uint8_t * data)483 static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data)
484 {
485 uint32_t val = 0;
486
487 /* Avoid Cppcheck Warning */
488 UNUSED(val);
489
490 #ifdef UART
491 if (UART == (Uart*)p_usart) {
492 while (uart_read((Uart*)p_usart, data));
493 }
494 #else
495 # ifdef UART0
496 if (UART0 == (Uart*)p_usart) {
497 while (uart_read((Uart*)p_usart, data));
498 }
499 # endif
500 # ifdef UART1
501 if (UART1 == (Uart*)p_usart) {
502 while (uart_read((Uart*)p_usart, data));
503 }
504 # endif
505 # ifdef UART2
506 if (UART2 == (Uart*)p_usart) {
507 while (uart_read((Uart*)p_usart, data));
508 }
509 # endif
510 # ifdef UART3
511 if (UART3 == (Uart*)p_usart) {
512 while (uart_read((Uart*)p_usart, data));
513 }
514 # endif
515 #endif /* ifdef UART */
516
517
518 #ifdef USART
519 if (USART == p_usart) {
520 while (usart_read(p_usart, &val));
521 *data = (uint8_t)(val & 0xFF);
522 }
523 #else
524 # ifdef USART0
525 if (USART0 == p_usart) {
526 while (usart_read(p_usart, &val));
527 *data = (uint8_t)(val & 0xFF);
528 }
529 # endif
530 # ifdef USART1
531 if (USART1 == p_usart) {
532 while (usart_read(p_usart, &val));
533 *data = (uint8_t)(val & 0xFF);
534 }
535 # endif
536 # ifdef USART2
537 if (USART2 == p_usart) {
538 while (usart_read(p_usart, &val));
539 *data = (uint8_t)(val & 0xFF);
540 }
541 # endif
542 # ifdef USART3
543 if (USART3 == p_usart) {
544 while (usart_read(p_usart, &val));
545 *data = (uint8_t)(val & 0xFF);
546 }
547 # endif
548 # ifdef USART4
549 if (USART4 == p_usart) {
550 while (usart_read(p_usart, &val));
551 *data = (uint8_t)(val & 0xFF);
552 }
553 # endif
554 # ifdef USART5
555 if (USART5 == p_usart) {
556 while (usart_read(p_usart, &val));
557 *data = (uint8_t)(val & 0xFF);
558 }
559 # endif
560 # ifdef USART6
561 if (USART6 == p_usart) {
562 while (usart_read(p_usart, &val));
563 *data = (uint8_t)(val & 0xFF);
564 }
565 # endif
566 # ifdef USART7
567 if (USART7 == p_usart) {
568 while (usart_read(p_usart, &val));
569 *data = (uint8_t)(val & 0xFF);
570 }
571 # endif
572 #endif /* ifdef USART */
573
574 }
575
576 /**
577 * \brief Check if Received data is ready.
578 *
579 * \param p_usart Base address of the USART instance.
580 *
581 * \retval 1 One data has been received.
582 * \retval 0 No data has been received.
583 */
usart_serial_is_rx_ready(usart_if p_usart)584 static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart)
585 {
586 #ifdef UART
587 if (UART == (Uart*)p_usart) {
588 return uart_is_rx_ready((Uart*)p_usart);
589 }
590 #else
591 # ifdef UART0
592 if (UART0 == (Uart*)p_usart) {
593 return uart_is_rx_ready((Uart*)p_usart);
594 }
595 # endif
596 # ifdef UART1
597 if (UART1 == (Uart*)p_usart) {
598 return uart_is_rx_ready((Uart*)p_usart);
599 }
600 # endif
601 # ifdef UART2
602 if (UART2 == (Uart*)p_usart) {
603 return uart_is_rx_ready((Uart*)p_usart);
604 }
605 # endif
606 # ifdef UART3
607 if (UART3 == (Uart*)p_usart) {
608 return uart_is_rx_ready((Uart*)p_usart);
609 }
610 # endif
611 #endif /* ifdef UART */
612
613
614 #ifdef USART
615 if (USART == p_usart) {
616 return usart_is_rx_ready(p_usart);
617 }
618 #else
619 # ifdef USART0
620 if (USART0 == p_usart) {
621 return usart_is_rx_ready(p_usart);
622 }
623 # endif
624 # ifdef USART1
625 if (USART1 == p_usart) {
626 return usart_is_rx_ready(p_usart);
627 }
628 # endif
629 # ifdef USART2
630 if (USART2 == p_usart) {
631 return usart_is_rx_ready(p_usart);
632 }
633 # endif
634 # ifdef USART3
635 if (USART3 == p_usart) {
636 return usart_is_rx_ready(p_usart);
637 }
638 # endif
639 # ifdef USART4
640 if (USART4 == p_usart) {
641 return usart_is_rx_ready(p_usart);
642 }
643 # endif
644 # ifdef USART5
645 if (USART5 == p_usart) {
646 return usart_is_rx_ready(p_usart);
647 }
648 # endif
649 # ifdef USART6
650 if (USART6 == p_usart) {
651 return usart_is_rx_ready(p_usart);
652 }
653 # endif
654 # ifdef USART7
655 if (USART7 == p_usart) {
656 return usart_is_rx_ready(p_usart);
657 }
658 # endif
659 #endif /* ifdef USART */
660
661 return 0;
662 }
663
664 /**
665 * \brief Send a sequence of bytes to a USART device
666 *
667 * \param usart Base address of the USART instance.
668 * \param data data buffer to write
669 * \param len Length of data
670 *
671 */
672 status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
673 size_t len);
674
675 /**
676 * \brief Receive a sequence of bytes to a USART device
677 *
678 * \param usart Base address of the USART instance.
679 * \param data data buffer to write
680 * \param len Length of data
681 *
682 */
683 status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
684 size_t len);
685
686 #endif /* _UART_SERIAL_H_ */
687