1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <cbfs.h>
4 #include <console/console.h>
5 #include <device/dram/ddr3.h>
6 #include <gpio.h>
7 #include <soc/romstage.h>
8 #include <spd.h>
9 #include <string.h>
10 #include <baseboard/variant.h>
11
12 #include "spd_util.h"
13 #include "spd.h"
14
mainboard_print_spd_info(uint8_t spd[])15 static void mainboard_print_spd_info(uint8_t spd[])
16 {
17 const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
18 const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
19 const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
20 const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
21 const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
22 const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
23 const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
24 char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 };
25
26 int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
27 int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
28 int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
29 int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
30 int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
31 int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
32 int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
33
34 /* Module type */
35 printk(BIOS_INFO, "SPD: module type is ");
36 switch (spd[SPD_MEMORY_TYPE]) {
37 case SPD_MEMORY_TYPE_SDRAM_DDR3:
38 printk(BIOS_INFO, "DDR3\n");
39 break;
40 case SPD_MEMORY_TYPE_LPDDR3_INTEL:
41 printk(BIOS_INFO, "LPDDR3\n");
42 break;
43 default:
44 printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]);
45 break;
46 }
47
48 /* Module Part Number */
49 memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN);
50 spd_name[SPD_DDR3_PART_LEN] = 0;
51 printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
52
53 printk(BIOS_INFO,
54 "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
55 banks, ranks, rows, cols, capmb);
56 printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
57 devw, busw);
58
59 if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
60 /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
61 printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
62 capmb / 8 * busw / devw * ranks);
63 }
64 }
65
is_dual_channel(const int spd_index)66 __weak int is_dual_channel(const int spd_index)
67 {
68 /* default to dual channel */
69 return 1;
70 }
71
72 /* Copy SPD data for on-board memory */
spd_memory_init_params(FSPM_UPD * mupd,int spd_index)73 void spd_memory_init_params(FSPM_UPD *mupd, int spd_index)
74 {
75 FSP_M_CONFIG *mem_cfg;
76 mem_cfg = &mupd->FspmConfig;
77 uint8_t *spd_file;
78 size_t spd_file_len;
79
80 printk(BIOS_INFO, "SPD index %d\n", spd_index);
81
82 /* Load SPD data from CBFS */
83 spd_file = cbfs_map("spd.bin", &spd_file_len);
84 if (!spd_file)
85 die("SPD data not found.");
86
87 /* make sure we have at least one SPD in the file. */
88 if (spd_file_len < SPD_SIZE_MAX_DDR3)
89 die("Missing SPD data.");
90
91 /* Make sure we did not overrun the buffer */
92 if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
93 printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
94 spd_index = 1;
95 }
96
97 const size_t spd_offset = spd_index * SPD_SIZE_MAX_DDR3;
98 /* Make sure a valid SPD was found */
99 if (spd_file[spd_offset] == 0)
100 die("Invalid SPD data.");
101
102 /* Assume same memory in both channels */
103 mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset;
104 if (is_dual_channel(spd_index))
105 mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
106
107 mainboard_print_spd_info(spd_file + spd_offset);
108 }
109