1 /*
2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <common/debug.h>
10 #include <drivers/delay_timer.h>
11 #include <lib/mmio.h>
12 #include <platform_def.h>
13
14 #include "socfpga_f2sdram_manager.h"
15 #include "socfpga_mailbox.h"
16 #include "socfpga_plat_def.h"
17 #include "socfpga_reset_manager.h"
18 #include "socfpga_system_manager.h"
19
deassert_peripheral_reset(void)20 void deassert_peripheral_reset(void)
21 {
22 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
23 RSTMGR_FIELD(PER1, WATCHDOG0) |
24 RSTMGR_FIELD(PER1, WATCHDOG1) |
25 RSTMGR_FIELD(PER1, WATCHDOG2) |
26 RSTMGR_FIELD(PER1, WATCHDOG3) |
27 RSTMGR_FIELD(PER1, WATCHDOG4) |
28 RSTMGR_FIELD(PER1, L4SYSTIMER0) |
29 RSTMGR_FIELD(PER1, L4SYSTIMER1) |
30 RSTMGR_FIELD(PER1, SPTIMER0) |
31 RSTMGR_FIELD(PER1, SPTIMER1) |
32 RSTMGR_FIELD(PER1, I2C0) |
33 RSTMGR_FIELD(PER1, I2C1) |
34 RSTMGR_FIELD(PER1, I2C2) |
35 RSTMGR_FIELD(PER1, I2C3) |
36 RSTMGR_FIELD(PER1, I2C4) |
37 RSTMGR_FIELD(PER1, I3C0) |
38 RSTMGR_FIELD(PER1, I3C1) |
39 RSTMGR_FIELD(PER1, UART0) |
40 RSTMGR_FIELD(PER1, UART1) |
41 RSTMGR_FIELD(PER1, GPIO0) |
42 RSTMGR_FIELD(PER1, GPIO1));
43
44 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
45 RSTMGR_FIELD(PER0, SOFTPHY) |
46 RSTMGR_FIELD(PER0, EMAC0OCP) |
47 RSTMGR_FIELD(PER0, EMAC1OCP) |
48 RSTMGR_FIELD(PER0, EMAC2OCP) |
49 RSTMGR_FIELD(PER0, USB0OCP) |
50 RSTMGR_FIELD(PER0, USB1OCP) |
51 RSTMGR_FIELD(PER0, NANDOCP) |
52 RSTMGR_FIELD(PER0, SDMMCOCP) |
53 RSTMGR_FIELD(PER0, DMAOCP));
54
55 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
56 RSTMGR_FIELD(PER0, EMAC0) |
57 RSTMGR_FIELD(PER0, EMAC1) |
58 RSTMGR_FIELD(PER0, EMAC2) |
59 RSTMGR_FIELD(PER0, USB0) |
60 RSTMGR_FIELD(PER0, USB1) |
61 RSTMGR_FIELD(PER0, NAND) |
62 RSTMGR_FIELD(PER0, SDMMC) |
63 RSTMGR_FIELD(PER0, DMA) |
64 RSTMGR_FIELD(PER0, SPIM0) |
65 RSTMGR_FIELD(PER0, SPIM1) |
66 RSTMGR_FIELD(PER0, SPIS0) |
67 RSTMGR_FIELD(PER0, SPIS1) |
68 RSTMGR_FIELD(PER0, EMACPTP) |
69 RSTMGR_FIELD(PER0, DMAIF0) |
70 RSTMGR_FIELD(PER0, DMAIF1) |
71 RSTMGR_FIELD(PER0, DMAIF2) |
72 RSTMGR_FIELD(PER0, DMAIF3) |
73 RSTMGR_FIELD(PER0, DMAIF4) |
74 RSTMGR_FIELD(PER0, DMAIF5) |
75 RSTMGR_FIELD(PER0, DMAIF6) |
76 RSTMGR_FIELD(PER0, DMAIF7));
77
78 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
79 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
80 RSTMGR_FIELD(BRG, MPFE));
81 #endif
82 }
83
config_hps_hs_before_warm_reset(void)84 void config_hps_hs_before_warm_reset(void)
85 {
86 uint32_t or_mask = 0;
87
88 or_mask |= RSTMGR_HDSKEN_EMIF_FLUSH;
89 or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
90 or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
91 or_mask |= RSTMGR_HDSKEN_LWS2F_FLUSH;
92 or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
93 or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
94
95 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
96 }
97
poll_idle_status(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_ms)98 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
99 {
100 int time_out = delay_ms;
101
102 while (time_out-- > 0) {
103
104 if ((mmio_read_32(addr) & mask) == match) {
105 return 0;
106 }
107 udelay(1000);
108 }
109 return -ETIMEDOUT;
110 }
111
112 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
poll_idle_status_by_counter(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_ms)113 static int poll_idle_status_by_counter(uint32_t addr, uint32_t mask,
114 uint32_t match, uint32_t delay_ms)
115 {
116 int time_out = delay_ms;
117
118 while (time_out-- > 0) {
119
120 if ((mmio_read_32(addr) & mask) == match) {
121 return 0;
122 }
123
124 /* ToDo: Shall use udelay for product release */
125 for (int i = 0; i < 2000; i++) {
126 /* dummy delay */
127 }
128 }
129 return -ETIMEDOUT;
130 }
131 #endif
132
133 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
poll_idle_status_by_clkcycles(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_clk_cycles)134 static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask,
135 uint32_t match, uint32_t delay_clk_cycles)
136 {
137 int time_out = delay_clk_cycles;
138
139 while (time_out-- > 0) {
140
141 if ((mmio_read_32(addr) & mask) == match) {
142 return 0;
143 }
144 udelay(1);
145 }
146 return -ETIMEDOUT;
147 }
148 #endif
149
socfpga_s2f_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * noc_mask)150 static void socfpga_s2f_bridge_mask(uint32_t mask,
151 uint32_t *brg_mask,
152 uint32_t *noc_mask)
153 {
154 *brg_mask = 0;
155 *noc_mask = 0;
156
157 if ((mask & SOC2FPGA_MASK) != 0U) {
158 *brg_mask |= RSTMGR_FIELD(BRG, SOC2FPGA);
159 *noc_mask |= IDLE_DATA_SOC2FPGA;
160 }
161
162 if ((mask & LWHPS2FPGA_MASK) != 0U) {
163 *brg_mask |= RSTMGR_FIELD(BRG, LWHPS2FPGA);
164 *noc_mask |= IDLE_DATA_LWSOC2FPGA;
165 }
166 }
167
socfpga_f2s_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * f2s_idlereq,uint32_t * f2s_force_drain,uint32_t * f2s_en,uint32_t * f2s_idleack,uint32_t * f2s_respempty,uint32_t * f2s_cmdidle)168 static void socfpga_f2s_bridge_mask(uint32_t mask,
169 uint32_t *brg_mask,
170 uint32_t *f2s_idlereq,
171 uint32_t *f2s_force_drain,
172 uint32_t *f2s_en,
173 uint32_t *f2s_idleack,
174 uint32_t *f2s_respempty,
175 uint32_t *f2s_cmdidle)
176 {
177 *brg_mask = 0;
178 *f2s_idlereq = 0;
179 *f2s_force_drain = 0;
180 *f2s_en = 0;
181 *f2s_idleack = 0;
182 *f2s_respempty = 0;
183 *f2s_cmdidle = 0;
184
185 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
186 if ((mask & FPGA2SOC_MASK) != 0U) {
187 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
188 }
189 if ((mask & F2SDRAM0_MASK) != 0U) {
190 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
191 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
192 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
193 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
194 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
195 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
196 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE;
197 }
198 if ((mask & F2SDRAM1_MASK) != 0U) {
199 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
200 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
201 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
202 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
203 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK;
204 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY;
205 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM1_CMDIDLE;
206 }
207 if ((mask & F2SDRAM2_MASK) != 0U) {
208 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
209 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
210 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
211 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
212 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK;
213 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY;
214 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM2_CMDIDLE;
215 }
216 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
217 if (mask & FPGA2SOC_MASK) {
218 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
219 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
220 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
221 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
222 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
223 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
224 }
225 if (mask & F2SDRAM0_MASK) {
226 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
227 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
228 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
229 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
230 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
231 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
232 }
233 if (mask & F2SDRAM1_MASK) {
234 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
235 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
236 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
237 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
238 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK;
239 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY;
240 }
241 if (mask & F2SDRAM2_MASK) {
242 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
243 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
244 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
245 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
246 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK;
247 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY;
248 }
249 #else
250 if ((mask & FPGA2SOC_MASK) != 0U) {
251 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
252 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
253 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
254 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
255 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
256 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
257 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE;
258 }
259 #endif
260 }
261
socfpga_bridges_reset(uint32_t mask)262 int socfpga_bridges_reset(uint32_t mask)
263 {
264 int ret = 0;
265 int timeout = 300;
266 uint32_t brg_mask = 0;
267 uint32_t noc_mask = 0;
268 uint32_t f2s_idlereq = 0;
269 uint32_t f2s_force_drain = 0;
270 uint32_t f2s_en = 0;
271 uint32_t f2s_idleack = 0;
272 uint32_t f2s_respempty = 0;
273 uint32_t f2s_cmdidle = 0;
274
275 /* Reset s2f bridge */
276 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
277 if (brg_mask) {
278 if (mask & SOC2FPGA_MASK) {
279 /* Request handshake with SOC2FPGA bridge to clear traffic */
280 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
281 RSTMGR_HDSKREQ_S2F_FLUSH);
282
283 /* Wait for bridge to idle status */
284 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
285 RSTMGR_HDSKACK_S2F_FLUSH,
286 RSTMGR_HDSKACK_S2F_FLUSH, 300);
287 }
288
289 if (mask & LWHPS2FPGA_MASK) {
290 /* Request handshake with LWSOC2FPGA bridge to clear traffic */
291 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
292 RSTMGR_HDSKREQ_LWS2F_FLUSH);
293
294 /* Wait for bridge to idle status */
295 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
296 RSTMGR_HDSKACK_LWS2F_FLUSH,
297 RSTMGR_HDSKACK_LWS2F_FLUSH, 300);
298 }
299
300 if (ret < 0) {
301 ERROR("S2F Bridge reset: Timeout waiting for idle ack\n");
302 assert(false);
303 }
304
305 /* Assert reset to bridge */
306 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
307 brg_mask);
308
309 /* Clear idle requests to bridge */
310 if (mask & SOC2FPGA_MASK) {
311 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
312 RSTMGR_HDSKREQ_S2F_FLUSH);
313 }
314
315 if (mask & LWHPS2FPGA_MASK) {
316 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
317 RSTMGR_HDSKREQ_LWS2F_FLUSH);
318 }
319
320 /* When FPGA reconfig is complete */
321 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
322 }
323
324 /* Reset f2s bridge */
325 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
326 &f2s_force_drain, &f2s_en,
327 &f2s_idleack, &f2s_respempty,
328 &f2s_cmdidle);
329
330 if (brg_mask) {
331 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
332 RSTMGR_HDSKEN_FPGAHSEN);
333
334 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
335 RSTMGR_HDSKREQ_FPGAHSREQ);
336
337 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
338 RSTMGR_HDSKACK_FPGAHSREQ,
339 RSTMGR_HDSKACK_FPGAHSREQ, 300);
340
341 if (ret < 0) {
342 ERROR("F2S Bridge disable: Timeout waiting for idle req\n");
343 assert(false);
344 }
345
346 /* Disable f2s bridge */
347 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
348 f2s_en);
349 udelay(5);
350
351 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
352 f2s_force_drain);
353 udelay(5);
354
355 do {
356 /* Read response queue status to ensure it is empty */
357 uint32_t idle_status;
358
359 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
360 SIDEBANDMGR_FLAGINSTATUS0));
361 if (idle_status & f2s_respempty) {
362 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
363 SIDEBANDMGR_FLAGINSTATUS0));
364 if (idle_status & f2s_respempty) {
365 break;
366 }
367 }
368 udelay(1000);
369 } while (timeout-- > 0);
370
371 /* Assert reset to f2s bridge */
372 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
373 brg_mask);
374
375 /* Clear idle request to FPGA */
376 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
377 RSTMGR_HDSKREQ_FPGAHSREQ);
378
379 /* Clear idle request to MPFE */
380 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
381 f2s_idlereq);
382
383 /* When FPGA reconfig is complete */
384 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
385
386 /* Enable f2s bridge */
387 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
388 f2s_idlereq);
389
390 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(
391 SIDEBANDMGR_FLAGINSTATUS0), f2s_idleack, 0, 300);
392 if (ret < 0) {
393 ERROR("F2S bridge enable: Timeout waiting for idle ack");
394 assert(false);
395 }
396
397 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
398 f2s_force_drain);
399 udelay(5);
400
401 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
402 f2s_en);
403 udelay(5);
404 }
405
406 return ret;
407 }
408
socfpga_bridges_enable(uint32_t mask)409 int socfpga_bridges_enable(uint32_t mask)
410 {
411 int ret = 0;
412 int ret_hps = 0;
413 uint32_t brg_mask = 0;
414 uint32_t noc_mask = 0;
415 uint32_t f2s_idlereq = 0;
416 uint32_t f2s_force_drain = 0;
417 uint32_t f2s_en = 0;
418 uint32_t f2s_idleack = 0;
419 uint32_t f2s_respempty = 0;
420 uint32_t f2s_cmdidle = 0;
421 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
422 uint32_t delay = 0;
423 #endif
424
425 /* Enable s2f bridge */
426 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
427 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
428 /* Enable SOC2FPGA bridge */
429 if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) {
430 /*
431 * To request handshake
432 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 1
433 */
434 VERBOSE("Set S2F hdskreq ...\n");
435 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
436 RSTMGR_HDSKREQ_SOC2FPGAREQ);
437
438 /*
439 * To poll idle status
440 * Read Reset Manager hdskack[soc2fpga] = 1
441 */
442 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
443 RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK,
444 300);
445
446 if (ret < 0) {
447 ERROR("S2F bridge enable: Timeout hdskack\n");
448 }
449
450 /*
451 * To clear idle request
452 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
453 */
454 VERBOSE("Clear S2F hdskreq ...\n");
455 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
456 RSTMGR_HDSKREQ_SOC2FPGAREQ);
457
458 /*
459 * To assert reset
460 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
461 */
462 VERBOSE("Assert S2F ...\n");
463 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
464 RSTMGR_BRGMODRST_SOC2FPGA);
465
466 /* ToDo: Shall use udelay for product release */
467 for (delay = 0; delay < 1000; delay++) {
468 /* dummy delay */
469 }
470
471 /*
472 * To deassert reset
473 * Write Reset Manager brgmodrst[soc2fpga] = 0
474 */
475 VERBOSE("Deassert S2F ...\n");
476 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
477 RSTMGR_BRGMODRST_SOC2FPGA);
478 }
479
480 /* Enable LWSOC2FPGA bridge */
481 if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
482 /*
483 * To request handshake
484 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1
485 */
486 VERBOSE("Set LWS2F hdskreq ...\n");
487 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
488 RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
489
490 /*
491 * To poll idle status
492 * Read Reset Manager hdskack[lwsoc2fpga] = 1
493 */
494 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
495 RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK,
496 300);
497
498 if (ret < 0) {
499 ERROR("LWS2F bridge enable: Timeout hdskack\n");
500 }
501
502 /*
503 * To clear idle request
504 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
505 */
506 VERBOSE("Clear LWS2F hdskreq ...\n");
507 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
508 RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
509
510 /*
511 * To assert reset
512 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
513 */
514 VERBOSE("Assert LWS2F ...\n");
515 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
516 RSTMGR_BRGMODRST_LWHPS2FPGA);
517
518 /* ToDo: Shall use udelay for product release */
519 for (delay = 0; delay < 1000; delay++) {
520 /* dummy delay */
521 }
522
523 /*
524 * To deassert reset
525 * Write Reset Manager brgmodrst[lwsoc2fpga] = 0
526 */
527 VERBOSE("Deassert LWS2F ...\n");
528 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
529 RSTMGR_BRGMODRST_LWHPS2FPGA);
530 }
531 #else
532 if (brg_mask != 0U) {
533 /* Clear idle request */
534 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR),
535 noc_mask);
536
537 /* De-assert all bridges */
538 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
539
540 /* Wait until idle ack becomes 0 */
541 ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
542 noc_mask, 0, 300);
543 if (ret_hps < 0) {
544 ERROR("S2F bridge enable: Timeout idle ack\n");
545 }
546 }
547 #endif
548
549 /* Enable f2s bridge */
550 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
551 &f2s_force_drain, &f2s_en,
552 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
553 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
554 /* Enable FPGA2SOC bridge */
555 if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
556 /*
557 * To request handshake
558 * Write Reset Manager hdsken[fpgahsen] = 1
559 */
560 VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
561 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
562
563 /*
564 * To request handshake
565 * Write Reset Manager hdskreq[fpgahsreq] = 1
566 */
567 VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
568 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
569
570 /*
571 * To poll idle status
572 * Read Reset Manager hdskack[fpgahsack] = 1
573 */
574 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
575 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
576 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
577 300);
578
579 if (ret < 0) {
580 ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n");
581 }
582
583 /*
584 * To fence and drain traffic
585 * Write Reset Manager hdskreq[f2s_flush_req] = 1
586 */
587 VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
588 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
589 RSTMGR_HDSKREQ_FPGA2SOCREQ);
590
591 /*
592 * To poll idle status
593 * Read Reset Manager hdskack[f2s_flush_ack] = 1
594 */
595 VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
596 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
597 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
598 300);
599
600 if (ret < 0) {
601 ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n");
602 }
603
604 /*
605 * To clear idle request
606 * Write Reset Manager hdskreq[fpgahsreq] = 1
607 */
608 VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
609 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
610
611 /*
612 * To clear idle request
613 * Write Reset Manager hdskreq[f2s_flush_req] = 1
614 */
615 VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
616 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
617 RSTMGR_HDSKREQ_FPGA2SOCREQ);
618
619 /*
620 * To poll idle status
621 * Read Reset Manager hdskack[f2s_flush_ack] = 0
622 */
623 VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
624 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
625 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
626 300);
627
628 if (ret < 0) {
629 ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
630 }
631
632 /*
633 * To poll idle status
634 * Read Reset Manager hdskack[fpgahsack] = 0
635 */
636 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
637 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
638 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
639 300);
640
641 if (ret < 0) {
642 ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
643 }
644
645 /*
646 * To assert reset
647 * Write Reset Manager brgmodrst[fpga2soc] = 1
648 */
649 VERBOSE("Assert F2S ...\n");
650 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
651
652 /* ToDo: Shall use udelay for product release */
653 for (delay = 0; delay < 1000; delay++) {
654 /* dummy delay */
655 }
656
657 /*
658 * To deassert reset
659 * Write Reset Manager brgmodrst[fpga2soc] = 0
660 */
661 VERBOSE("Deassert F2S ...\n");
662 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
663
664 /* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
665 VERBOSE("Deassert F2S f2soc_enable ...\n");
666 mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
667 SYSMGR_F2S_BRIDGE_CTRL_EN);
668 }
669
670 /* Enable FPGA2SDRAM bridge */
671 if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
672 /*
673 * To request handshake
674 * Write Reset Manager hdsken[fpgahsen] = 1
675 */
676 VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
677 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
678
679 /*
680 * To request handshake
681 * Write Reset Manager hdskreq[fpgahsreq] = 1
682 */
683 VERBOSE("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
684 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
685
686 /*
687 * To poll idle status
688 * Read Reset Manager hdskack[fpgahsack] = 1
689 */
690 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
691 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
692 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
693 300);
694
695 if (ret < 0) {
696 ERROR("F2SDRAM bridge fpga handshake fpgahsreq: Timeout\n");
697 }
698
699 /*
700 * To fence and drain traffic
701 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
702 */
703 VERBOSE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
704 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
705 RSTMGR_HDSKREQ_F2SDRAM0REQ);
706
707 /*
708 * To poll idle status
709 * Read Reset Manager hdskack[f2sdram_flush_ack] = 1
710 */
711 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
712 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
713 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK,
714 300);
715
716 if (ret < 0) {
717 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_req: Timeout\n");
718 }
719
720 /*
721 * To clear idle request
722 * Write Reset Manager hdskreq[fpgahsreq] = 1
723 */
724 VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
725 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
726
727 /*
728 * To clear idle request
729 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
730 */
731 VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
732 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
733
734 /*
735 * To poll idle status
736 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
737 */
738 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
739 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
740 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
741 300);
742
743 if (ret < 0) {
744 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
745 }
746
747 /*
748 * To poll idle status
749 * Read Reset Manager hdskack[fpgahsack] = 0
750 */
751 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
752 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
753 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
754 300);
755
756 if (ret < 0) {
757 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
758 }
759
760 /*
761 * To assert reset
762 * Write Reset Manager brgmodrst[fpga2sdram] = 1
763 */
764 VERBOSE("Assert F2SDRAM ...\n");
765 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
766 RSTMGR_BRGMODRST_F2SSDRAM0);
767
768 /* ToDo: Shall use udelay for product release */
769 for (delay = 0; delay < 1000; delay++) {
770 /* dummy delay */
771 }
772
773 /*
774 * To deassert reset
775 * Write Reset Manager brgmodrst[fpga2sdram] = 0
776 */
777 VERBOSE("Deassert F2SDRAM ...\n");
778 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
779 RSTMGR_BRGMODRST_F2SSDRAM0);
780
781 /*
782 * Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0
783 * f2s_ready_latency_enable
784 */
785 VERBOSE("Clear F2SDRAM f2s_ready_latency_enable ...\n");
786 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
787 FLAGOUTCLR0_F2SDRAM0_ENABLE);
788 }
789 #else
790 if (brg_mask != 0U) {
791 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
792
793 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
794 f2s_idlereq);
795
796 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0),
797 f2s_idleack, 0, 300);
798
799 if (ret < 0) {
800 ERROR("F2S bridge enable: Timeout idle ack");
801 }
802
803 /* Clear the force drain */
804 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
805 f2s_force_drain);
806 udelay(5);
807
808 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
809 f2s_en);
810 udelay(5);
811 }
812 #endif
813 ret = ret | ret_hps;
814 return ret;
815 }
816
socfpga_bridge_nongraceful_disable(uint32_t mask)817 int socfpga_bridge_nongraceful_disable(uint32_t mask)
818 {
819 int ret = 0;
820 int timeout = 1000;
821 uint32_t brg_mask = 0;
822 uint32_t f2s_idlereq = 0;
823 uint32_t f2s_force_drain = 0;
824 uint32_t f2s_en = 0;
825 uint32_t f2s_idleack = 0;
826 uint32_t f2s_respempty = 0;
827 uint32_t f2s_cmdidle = 0;
828
829 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
830 &f2s_force_drain, &f2s_en,
831 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
832
833 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
834 f2s_idlereq);
835
836 /* Time out Error - Bus is still active */
837 /* Performing a non-graceful shutdown with Force drain */
838 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
839 f2s_force_drain);
840
841 ret = -ETIMEDOUT;
842 do {
843 /* Read response queue status to ensure it is empty */
844 uint32_t idle_status;
845
846 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0));
847 if ((idle_status & f2s_respempty) != 0U) {
848 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0));
849 if ((idle_status & f2s_respempty) != 0U) {
850 /* No time-out we are good! */
851 ret = 0;
852 break;
853 }
854 }
855
856 asm("nop");
857
858 } while (timeout-- > 0);
859
860 return ret;
861 }
862
socfpga_bridges_disable(uint32_t mask)863 int socfpga_bridges_disable(uint32_t mask)
864 {
865 int ret = 0;
866 uint32_t brg_mask = 0;
867 uint32_t noc_mask = 0;
868 uint32_t f2s_idlereq = 0;
869 uint32_t f2s_force_drain = 0;
870 uint32_t f2s_en = 0;
871 uint32_t f2s_idleack = 0;
872 uint32_t f2s_respempty = 0;
873 uint32_t f2s_cmdidle = 0;
874 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
875 uint32_t delay = 0;
876 #endif
877
878
879 /* Disable s2f bridge */
880 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
881 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
882 /* Disable SOC2FPGA bridge */
883 if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) {
884 /*
885 * To clear handshake
886 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
887 */
888 VERBOSE("Set S2F hdskreq ...\n");
889 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
890 RSTMGR_HDSKREQ_SOC2FPGAREQ);
891
892 /*
893 * To poll idle status
894 * Read Reset Manager hdskack[soc2fpga] = 0
895 */
896 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
897 RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK_DASRT,
898 300);
899
900 if (ret < 0) {
901 ERROR("S2F bridge enable: Timeout hdskack\n");
902 }
903
904 /*
905 * To assert reset
906 * Write Reset Manager brgmodrst[soc2fpga] = 1
907 */
908 VERBOSE("Assert S2F ...\n");
909 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
910 RSTMGR_BRGMODRST_SOC2FPGA);
911
912 /* ToDo: Shall use udelay for product release */
913 for (delay = 0; delay < 1000; delay++) {
914 /* dummy delay */
915 }
916 }
917
918 /* Disable LWSOC2FPGA bridge */
919 if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
920 /*
921 * To clear handshake
922 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
923 */
924 VERBOSE("Set LWS2F hdskreq ...\n");
925 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
926 RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
927
928 /*
929 * To poll idle status
930 * Read Reset Manager hdskack[lwsoc2fpga] = 0
931 */
932 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
933 RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT,
934 300);
935
936 if (ret < 0) {
937 ERROR("LWS2F bridge enable: Timeout hdskack\n");
938 }
939
940 /*
941 * To assert reset
942 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
943 */
944 VERBOSE("Assert LWS2F ...\n");
945 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
946 RSTMGR_BRGMODRST_LWHPS2FPGA);
947
948 /* ToDo: Shall use udelay for product release */
949 for (delay = 0; delay < 1000; delay++) {
950 /* dummy delay */
951 }
952 }
953 #else
954 if (brg_mask != 0U) {
955 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET),
956 noc_mask);
957
958 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
959
960 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
961 noc_mask, noc_mask, 300);
962 if (ret < 0) {
963 ERROR("S2F Bridge disable: Timeout idle ack\n");
964 }
965
966 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
967 noc_mask, noc_mask, 300);
968 if (ret < 0) {
969 ERROR("S2F Bridge disable: Timeout idle status\n");
970 }
971
972 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
973
974 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0);
975 }
976 #endif
977
978 /* Disable f2s bridge */
979 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
980 &f2s_force_drain, &f2s_en,
981 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
982 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
983 /* Disable FPGA2SOC bridge */
984 if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
985 /*
986 * To request handshake
987 * Write Reset Manager hdsken[fpgahsen] = 1
988 */
989 VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
990 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
991
992 /*
993 * To clear handshake request
994 * Write Reset Manager hdskreq[fpgahsreq] = 0
995 */
996 VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
997 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
998
999 /*
1000 * To clear handshake request
1001 * Write Reset Manager hdskreq[f2s_flush_req] = 0
1002 */
1003 VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
1004 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1005 RSTMGR_HDSKREQ_FPGA2SOCREQ);
1006
1007 /*
1008 * To poll idle status
1009 * Read Reset Manager hdskack[f2s_flush_ack] = 0
1010 */
1011 VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
1012 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
1013 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
1014 300);
1015
1016 if (ret < 0) {
1017 ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
1018 }
1019
1020 /*
1021 * To poll idle status
1022 * Read Reset Manager hdskack[fpgahsack] = 0
1023 */
1024 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
1025 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
1026 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
1027 300);
1028
1029 if (ret < 0) {
1030 ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
1031 }
1032
1033 /*
1034 * To assert reset
1035 * Write Reset Manager brgmodrst[fpga2soc] = 1
1036 */
1037 VERBOSE("Assert F2S ...\n");
1038 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
1039
1040 /* ToDo: Shall use udelay for product release */
1041 for (delay = 0; delay < 1000; delay++) {
1042 /* dummy delay */
1043 }
1044
1045 /* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
1046 VERBOSE("Assert F2S f2soc_enable ...\n");
1047 mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
1048 SYSMGR_F2S_BRIDGE_CTRL_EN);
1049 }
1050
1051 /* Disable FPGA2SDRAM bridge */
1052 if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
1053 /*
1054 * To request handshake
1055 * Write Reset Manager hdsken[fpgahsen] = 1
1056 */
1057 VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
1058 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
1059
1060 /*
1061 * To clear handshake request
1062 * Write Reset Manager hdskreq[fpgahsreq] = 0
1063 */
1064 VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
1065 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
1066
1067 /*
1068 * To clear handshake request
1069 * Write Reset Manager hdskreq[f2sdram_flush_req] = 0
1070 */
1071 VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
1072 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
1073
1074 /*
1075 * To poll idle status
1076 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
1077 */
1078 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
1079 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
1080 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
1081 300);
1082
1083 if (ret < 0) {
1084 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
1085 }
1086
1087 /*
1088 * To poll idle status
1089 * Read Reset Manager hdskack[fpgahsack] = 0
1090 */
1091 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
1092 ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
1093 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
1094 300);
1095
1096 if (ret < 0) {
1097 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
1098 }
1099
1100 /*
1101 * To assert reset
1102 * Write Reset Manager brgmodrst[fpga2sdram] = 1
1103 */
1104 VERBOSE("Assert F2SDRAM ...\n");
1105 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1106 RSTMGR_BRGMODRST_F2SSDRAM0);
1107
1108 /* ToDo: Shall use udelay for product release */
1109 for (delay = 0; delay < 1000; delay++) {
1110 /* dummy delay */
1111 }
1112
1113 /*
1114 * Assert fpga2sdram_manager_main_SidebandManager_FlagOutClr0
1115 * f2s_ready_latency_enable
1116 */
1117 VERBOSE("Assert F2SDRAM f2s_ready_latency_enable ...\n");
1118 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1119 FLAGOUTCLR0_F2SDRAM0_ENABLE);
1120 }
1121 #else
1122 if (brg_mask != 0U) {
1123
1124 if (mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST)) & brg_mask) {
1125 /* Bridge cannot be reset twice */
1126 return 0;
1127 }
1128
1129 /* Starts the fence and drain traffic from F2SDRAM to MPFE */
1130 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
1131 RSTMGR_HDSKEN_FPGAHSEN);
1132 udelay(5);
1133 /* Ignoring FPGA ACK as it will time-out */
1134 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1135 RSTMGR_HDSKREQ_FPGAHSREQ);
1136
1137 ret = poll_idle_status_by_clkcycles(SOCFPGA_RSTMGR(HDSKACK),
1138 RSTMGR_HDSKACK_FPGAHSREQ,
1139 RSTMGR_HDSKACK_FPGAHSREQ, 1000);
1140
1141 /* DISABLE F2S Bridge */
1142 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1143 f2s_en);
1144 udelay(5);
1145
1146 ret = socfpga_bridge_nongraceful_disable(mask);
1147
1148 /* Bridge reset */
1149 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
1150 /* Software must never write a 0x1 to FPGA2SOC_M0ASK bit */
1151 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1152 brg_mask & ~RSTMGR_FIELD(BRG, FPGA2SOC));
1153 #else
1154 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1155 brg_mask);
1156 #endif
1157 /* Re-enable traffic to SDRAM*/
1158 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1159 RSTMGR_HDSKREQ_FPGAHSREQ);
1160
1161 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1162 f2s_idlereq);
1163 }
1164 #endif
1165
1166 return ret;
1167 }
1168
1169 /* CPUxRESETBASELOW */
socfpga_cpu_reset_base(unsigned int cpu_id)1170 int socfpga_cpu_reset_base(unsigned int cpu_id)
1171 {
1172 int ret = 0;
1173 uint32_t entrypoint = 0;
1174
1175 ret = socfpga_cpurstrelease(cpu_id);
1176
1177 if (ret < 0) {
1178 return RSTMGR_RET_ERROR;
1179 }
1180
1181 if (ret == RSTMGR_RET_OK) {
1182
1183 switch (cpu_id) {
1184 case 0:
1185 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_0);
1186 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_0) << 24;
1187 break;
1188
1189 case 1:
1190 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_1);
1191 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_1) << 24;
1192 break;
1193
1194 case 2:
1195 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_2);
1196 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_2) << 24;
1197 break;
1198
1199 case 3:
1200 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_3);
1201 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_3) << 24;
1202 break;
1203
1204 default:
1205 break;
1206 }
1207
1208 mmio_write_64(PLAT_SEC_ENTRY, entrypoint);
1209 }
1210
1211 return RSTMGR_RET_OK;
1212 }
1213
1214 /* CPURSTRELEASE */
socfpga_cpurstrelease(unsigned int cpu_id)1215 int socfpga_cpurstrelease(unsigned int cpu_id)
1216 {
1217 unsigned int timeout = 0;
1218
1219 do {
1220 /* Read response queue status to ensure it is empty */
1221 uint32_t cpurstrelease_status;
1222
1223 cpurstrelease_status = mmio_read_32(SOCFPGA_RSTMGR(CPURSTRELEASE));
1224
1225 if ((cpurstrelease_status & RSTMGR_CPUSTRELEASE_CPUx) == cpu_id) {
1226 return RSTMGR_RET_OK;
1227 }
1228 udelay(1000);
1229 } while (timeout-- > 0);
1230
1231 return RSTMGR_RET_ERROR;
1232 }
1233