1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi.h>
4 #include <amdblocks/acpi.h>
5 #include <amdblocks/agesawrapper_call.h>
6 #include <amdblocks/agesawrapper.h>
7 #include <amdblocks/biosram.h>
8 #include <amdblocks/post_codes.h>
9 #include <amdblocks/psp.h>
10 #include <arch/romstage.h>
11 #include <cbmem.h>
12 #include <commonlib/helpers.h>
13 #include <console/console.h>
14 #include <cpu/amd/mtrr.h>
15 #include <cpu/cpu.h>
16 #include <cpu/x86/msr.h>
17 #include <cpu/x86/mtrr.h>
18 #include <cpu/x86/smm.h>
19 #include <device/device.h>
20 #include <device/pci_ops.h>
21 #include <elog.h>
22 #include <program_loading.h>
23 #include <romstage_common.h>
24 #include <romstage_handoff.h>
25 #include <soc/iomap.h>
26 #include <soc/northbridge.h>
27 #include <soc/pci_devs.h>
28 #include <soc/southbridge.h>
29 #include <stdint.h>
30
31 #include "chip.h"
32
mainboard_romstage_entry(void)33 void __weak mainboard_romstage_entry(void)
34 {
35 /* By default, don't do anything */
36 }
37
agesa_call(void)38 static void agesa_call(void)
39 {
40 post_code(POSTCODE_AGESA_AMDINITRESET);
41 do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
42
43 post_code(POSTCODE_AGESA_AMDINITEARLY);
44 /* APs will not exit amdinitearly */
45 do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
46 }
47
bsp_agesa_call(void)48 static void bsp_agesa_call(void)
49 {
50 set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */
51 agesa_call();
52 }
romstage_main(void)53 void __noreturn romstage_main(void)
54 {
55 msr_t base, mask;
56 msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
57 int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
58 int s3_resume = acpi_is_wakeup_s3();
59 int i;
60
61 soc_enable_psp_early();
62 if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
63 psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
64
65 mainboard_romstage_entry();
66 elog_boot_notify(s3_resume);
67
68 bsp_agesa_call();
69
70 if (!s3_resume) {
71 post_code(POSTCODE_AGESA_AMDINITPOST);
72 do_agesawrapper(AMD_INIT_POST, "amdinitpost");
73
74 post_code(POSTCODE_AGESA_AMDINITPOST_DONE);
75 /*
76 * TODO: This is a hack to work around current AGESA behavior.
77 * AGESA needs to change to reflect that coreboot owns
78 * the MTRRs.
79 *
80 * After setting up DRAM, AGESA also completes the configuration
81 * of the MTRRs, setting regions to WB. Anything written to
82 * memory between now and when CAR is dismantled will be
83 * in cache and lost. For now, set the regions UC to ensure
84 * the writes get to DRAM.
85 */
86 for (i = 0 ; i < vmtrrs ; i++) {
87 base = rdmsr(MTRR_PHYS_BASE(i));
88 mask = rdmsr(MTRR_PHYS_MASK(i));
89 if (!(mask.lo & MTRR_PHYS_MASK_VALID))
90 continue;
91
92 if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
93 base.lo &= ~0x7;
94 base.lo |= MTRR_TYPE_UNCACHEABLE;
95 wrmsr(MTRR_PHYS_BASE(i), base);
96 }
97 }
98 /* Disable WB from to region 4GB-TOM2. */
99 msr_t sys_cfg = rdmsr(SYSCFG_MSR);
100 sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
101 wrmsr(SYSCFG_MSR, sys_cfg);
102 } else {
103 printk(BIOS_INFO, "S3 detected\n");
104 post_code(POSTCODE_AGESA_AMDINITRESUME);
105 do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
106
107 post_code(POSTCODE_AGESA_AMDINITRESUME_DONE);
108 }
109
110 post_code(POSTCODE_PSP_NOTIFY_DRAM);
111 psp_notify_dram();
112
113 post_code(POSTCODE_PSP_NOTIFY_DRAM_DONE);
114 if (cbmem_recovery(s3_resume))
115 printk(BIOS_CRIT, "Failed to recover cbmem\n");
116 if (romstage_handoff_init(s3_resume))
117 printk(BIOS_ERR, "Failed to set romstage handoff data\n");
118
119 if (CONFIG(SMM_TSEG))
120 smm_list_regions();
121
122 post_code(POSTCODE_ROMSTAGE_RUN_POSTCAR);
123 prepare_and_run_postcar();
124 }
125
fill_postcar_frame(struct postcar_frame * pcf)126 void fill_postcar_frame(struct postcar_frame *pcf)
127 {
128 const uintptr_t top_of_ram = cbmem_top();
129 postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
130
131 /* Cache the TSEG region */
132 postcar_enable_tseg_cache(pcf);
133 }
134
SetMemParams(AMD_POST_PARAMS * PostParams)135 void SetMemParams(AMD_POST_PARAMS *PostParams)
136 {
137 const struct soc_amd_stoneyridge_config *cfg;
138 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
139
140 if (!dev || !dev->chip_info) {
141 printk(BIOS_ERR, "Cannot find SoC devicetree config\n");
142 /* In case of a BIOS error, only attempt to set UMA. */
143 PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ?
144 UMA_AUTO : UMA_NONE;
145 return;
146 }
147
148 cfg = dev->chip_info;
149
150 PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
151
152 switch (cfg->uma_mode) {
153 case UMAMODE_NONE:
154 PostParams->MemConfig.UmaMode = UMA_NONE;
155 break;
156 case UMAMODE_SPECIFIED_SIZE:
157 PostParams->MemConfig.UmaMode = UMA_SPECIFIED;
158 /* 64 KiB blocks. */
159 PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB);
160 break;
161 case UMAMODE_AUTO_LEGACY:
162 PostParams->MemConfig.UmaMode = UMA_AUTO;
163 PostParams->MemConfig.UmaVersion = UMA_LEGACY;
164 break;
165 case UMAMODE_AUTO_NON_LEGACY:
166 PostParams->MemConfig.UmaMode = UMA_AUTO;
167 PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY;
168 break;
169 }
170 }
171
soc_customize_init_early(AMD_EARLY_PARAMS * InitEarly)172 void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
173 {
174 const struct soc_amd_stoneyridge_config *cfg;
175 const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
176 struct _PLATFORM_CONFIGURATION *platform;
177
178 if (!dev || !dev->chip_info) {
179 printk(BIOS_WARNING, "Cannot find SoC devicetree"
180 " config, STAPM unchanged\n");
181 return;
182 }
183 cfg = dev->chip_info;
184 platform = &InitEarly->PlatformConfig;
185 if ((cfg->stapm_percent) && (cfg->stapm_time_ms) &&
186 (cfg->stapm_power_mw)) {
187 platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
188 platform->PlatStapmConfig.CfgStapmTimeConstant =
189 cfg->stapm_time_ms;
190 platform->PkgPwrLimitDC = cfg->stapm_power_mw;
191 platform->PkgPwrLimitAC = cfg->stapm_power_mw;
192 platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
193 }
194
195 /* Make binaryPi use ACPI_CSTATE_CONTROL as C state control IO range. It gets written
196 into MSR_CSTATE_ADDRESS and used in the _CST packages in the PSTATE SSDT. */
197 platform->CStateIoBaseAddress = ACPI_CSTATE_CONTROL;
198 }
199
migrate_power_state(int is_recovery)200 static void migrate_power_state(int is_recovery)
201 {
202 struct chipset_power_state *state;
203 state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
204 if (state) {
205 acpi_fill_pm_gpe_state(&state->gpe_state);
206 acpi_pm_gpe_add_events_print_events();
207 }
208 }
209 CBMEM_CREATION_HOOK(migrate_power_state);
210