1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v13_0.h"
29 #include "smu13_driver_if_v13_0_5.h"
30 #include "smu_v13_0_5_ppt.h"
31 #include "smu_v13_0_5_ppsmc.h"
32 #include "smu_v13_0_5_pmfw.h"
33 #include "smu_cmn.h"
34
35 /*
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
39 */
40 #undef pr_err
41 #undef pr_warn
42 #undef pr_info
43 #undef pr_debug
44
45 #define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
46 #define mmMP1_C2PMSG_2_BASE_IDX 0
47
48 #define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
49 #define mmMP1_C2PMSG_34_BASE_IDX 0
50
51 #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
52 #define mmMP1_C2PMSG_33_BASE_IDX 0
53
54 #define FEATURE_MASK(feature) (1ULL << feature)
55 #define SMC_DPM_FEATURE ( \
56 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
57 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
58 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
59 FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
60 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
61 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
62 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
63 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
64 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
65
66 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
67 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
68 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
69 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
70 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
71 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
72 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
73 MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1),
74 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
75 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
76 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
79 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
80 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
81 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
82 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
83 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
84 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
85 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
86 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
87 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
88 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
89 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
90 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91 };
92
93 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = {
94 FEA_MAP(DATA_CALCULATION),
95 FEA_MAP(PPT),
96 FEA_MAP(TDC),
97 FEA_MAP(THERMAL),
98 FEA_MAP(PROCHOT),
99 FEA_MAP(CCLK_DPM),
100 FEA_MAP_REVERSE(FCLK),
101 FEA_MAP(LCLK_DPM),
102 FEA_MAP(DF_CSTATES),
103 FEA_MAP(FAN_CONTROLLER),
104 FEA_MAP(CPPC),
105 FEA_MAP_HALF_REVERSE(GFX),
106 FEA_MAP(DS_GFXCLK),
107 FEA_MAP(S0I3),
108 FEA_MAP(VCN_DPM),
109 FEA_MAP(DS_VCN),
110 FEA_MAP(DCFCLK_DPM),
111 FEA_MAP(ATHUB_PG),
112 FEA_MAP_REVERSE(SOCCLK),
113 FEA_MAP(SHUBCLK_DPM),
114 FEA_MAP(GFXOFF),
115 };
116
117 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = {
118 TAB_MAP_VALID(WATERMARKS),
119 TAB_MAP_VALID(SMU_METRICS),
120 TAB_MAP_VALID(CUSTOM_DPM),
121 TAB_MAP_VALID(DPMCLOCKS),
122 };
123
smu_v13_0_5_init_smc_tables(struct smu_context * smu)124 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
125 {
126 struct smu_table_context *smu_table = &smu->smu_table;
127 struct smu_table *tables = smu_table->tables;
128
129 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
130 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
131 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
132 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
133 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
135
136 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
137 if (!smu_table->clocks_table)
138 goto err0_out;
139
140 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
141 if (!smu_table->metrics_table)
142 goto err1_out;
143 smu_table->metrics_time = 0;
144
145 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
146 if (!smu_table->watermarks_table)
147 goto err2_out;
148
149 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
150 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
151 if (!smu_table->gpu_metrics_table)
152 goto err3_out;
153
154 return 0;
155
156 err3_out:
157 kfree(smu_table->watermarks_table);
158 err2_out:
159 kfree(smu_table->metrics_table);
160 err1_out:
161 kfree(smu_table->clocks_table);
162 err0_out:
163 return -ENOMEM;
164 }
165
smu_v13_0_5_fini_smc_tables(struct smu_context * smu)166 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
167 {
168 struct smu_table_context *smu_table = &smu->smu_table;
169
170 kfree(smu_table->clocks_table);
171 smu_table->clocks_table = NULL;
172
173 kfree(smu_table->metrics_table);
174 smu_table->metrics_table = NULL;
175
176 kfree(smu_table->watermarks_table);
177 smu_table->watermarks_table = NULL;
178
179 kfree(smu_table->gpu_metrics_table);
180 smu_table->gpu_metrics_table = NULL;
181
182 return 0;
183 }
184
smu_v13_0_5_system_features_control(struct smu_context * smu,bool en)185 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
186 {
187 struct amdgpu_device *adev = smu->adev;
188 int ret = 0;
189
190 if (!en && !adev->in_s0ix)
191 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
192
193 return ret;
194 }
195
smu_v13_0_5_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)196 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu,
197 bool enable,
198 int inst)
199 {
200 int ret = 0;
201
202 /* vcn dpm on is a prerequisite for vcn power gate messages */
203 if (enable)
204 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
205 0, NULL);
206 else
207 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
208 0, NULL);
209
210 return ret;
211 }
212
smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)213 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
214 {
215 int ret = 0;
216
217 if (enable)
218 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
219 0, NULL);
220 else
221 ret = smu_cmn_send_smc_msg_with_param(smu,
222 SMU_MSG_PowerDownJpeg, 0,
223 NULL);
224
225 return ret;
226 }
227
228
smu_v13_0_5_is_dpm_running(struct smu_context * smu)229 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
230 {
231 int ret = 0;
232 uint64_t feature_enabled;
233
234 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
235
236 if (ret)
237 return false;
238
239 return !!(feature_enabled & SMC_DPM_FEATURE);
240 }
241
smu_v13_0_5_mode_reset(struct smu_context * smu,int type)242 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
243 {
244 int ret = 0;
245
246 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
247 if (ret)
248 dev_err(smu->adev->dev, "Failed to mode reset!\n");
249
250 return ret;
251 }
252
smu_v13_0_5_mode2_reset(struct smu_context * smu)253 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
254 {
255 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
256 }
257
smu_v13_0_5_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)258 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
259 MetricsMember_t member,
260 uint32_t *value)
261 {
262 struct smu_table_context *smu_table = &smu->smu_table;
263
264 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
265 int ret = 0;
266
267 ret = smu_cmn_get_metrics_table(smu, NULL, false);
268 if (ret)
269 return ret;
270
271 switch (member) {
272 case METRICS_AVERAGE_GFXCLK:
273 *value = metrics->GfxclkFrequency;
274 break;
275 case METRICS_AVERAGE_SOCCLK:
276 *value = metrics->SocclkFrequency;
277 break;
278 case METRICS_AVERAGE_VCLK:
279 *value = metrics->VclkFrequency;
280 break;
281 case METRICS_AVERAGE_DCLK:
282 *value = metrics->DclkFrequency;
283 break;
284 case METRICS_AVERAGE_UCLK:
285 *value = metrics->MemclkFrequency;
286 break;
287 case METRICS_AVERAGE_GFXACTIVITY:
288 *value = metrics->GfxActivity / 100;
289 break;
290 case METRICS_AVERAGE_VCNACTIVITY:
291 *value = metrics->UvdActivity / 100;
292 break;
293 case METRICS_CURR_SOCKETPOWER:
294 *value = (metrics->CurrentSocketPower << 8) / 1000;
295 break;
296 case METRICS_TEMPERATURE_EDGE:
297 *value = metrics->GfxTemperature / 100 *
298 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
299 break;
300 case METRICS_TEMPERATURE_HOTSPOT:
301 *value = metrics->SocTemperature / 100 *
302 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
303 break;
304 case METRICS_THROTTLER_STATUS:
305 *value = metrics->ThrottlerStatus;
306 break;
307 case METRICS_VOLTAGE_VDDGFX:
308 *value = metrics->Voltage[0];
309 break;
310 case METRICS_VOLTAGE_VDDSOC:
311 *value = metrics->Voltage[1];
312 break;
313 default:
314 *value = UINT_MAX;
315 break;
316 }
317
318 return ret;
319 }
320
smu_v13_0_5_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)321 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
322 enum amd_pp_sensors sensor,
323 void *data, uint32_t *size)
324 {
325 int ret = 0;
326
327 if (!data || !size)
328 return -EINVAL;
329
330 switch (sensor) {
331 case AMDGPU_PP_SENSOR_GPU_LOAD:
332 ret = smu_v13_0_5_get_smu_metrics_data(smu,
333 METRICS_AVERAGE_GFXACTIVITY,
334 (uint32_t *)data);
335 *size = 4;
336 break;
337 case AMDGPU_PP_SENSOR_VCN_LOAD:
338 ret = smu_v13_0_5_get_smu_metrics_data(smu,
339 METRICS_AVERAGE_VCNACTIVITY,
340 (uint32_t *)data);
341 *size = 4;
342 break;
343 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
344 ret = smu_v13_0_5_get_smu_metrics_data(smu,
345 METRICS_CURR_SOCKETPOWER,
346 (uint32_t *)data);
347 *size = 4;
348 break;
349 case AMDGPU_PP_SENSOR_EDGE_TEMP:
350 ret = smu_v13_0_5_get_smu_metrics_data(smu,
351 METRICS_TEMPERATURE_EDGE,
352 (uint32_t *)data);
353 *size = 4;
354 break;
355 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
356 ret = smu_v13_0_5_get_smu_metrics_data(smu,
357 METRICS_TEMPERATURE_HOTSPOT,
358 (uint32_t *)data);
359 *size = 4;
360 break;
361 case AMDGPU_PP_SENSOR_GFX_MCLK:
362 ret = smu_v13_0_5_get_smu_metrics_data(smu,
363 METRICS_AVERAGE_UCLK,
364 (uint32_t *)data);
365 *(uint32_t *)data *= 100;
366 *size = 4;
367 break;
368 case AMDGPU_PP_SENSOR_GFX_SCLK:
369 ret = smu_v13_0_5_get_smu_metrics_data(smu,
370 METRICS_AVERAGE_GFXCLK,
371 (uint32_t *)data);
372 *(uint32_t *)data *= 100;
373 *size = 4;
374 break;
375 case AMDGPU_PP_SENSOR_VDDGFX:
376 ret = smu_v13_0_5_get_smu_metrics_data(smu,
377 METRICS_VOLTAGE_VDDGFX,
378 (uint32_t *)data);
379 *size = 4;
380 break;
381 case AMDGPU_PP_SENSOR_VDDNB:
382 ret = smu_v13_0_5_get_smu_metrics_data(smu,
383 METRICS_VOLTAGE_VDDSOC,
384 (uint32_t *)data);
385 *size = 4;
386 break;
387 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
388 ret = smu_v13_0_5_get_smu_metrics_data(smu,
389 METRICS_SS_APU_SHARE,
390 (uint32_t *)data);
391 *size = 4;
392 break;
393 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
394 ret = smu_v13_0_5_get_smu_metrics_data(smu,
395 METRICS_SS_DGPU_SHARE,
396 (uint32_t *)data);
397 *size = 4;
398 break;
399 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
400 default:
401 ret = -EOPNOTSUPP;
402 break;
403 }
404
405 return ret;
406 }
407
smu_v13_0_5_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)408 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
409 struct pp_smu_wm_range_sets *clock_ranges)
410 {
411 int i;
412 int ret = 0;
413 Watermarks_t *table = smu->smu_table.watermarks_table;
414
415 if (!table || !clock_ranges)
416 return -EINVAL;
417
418 if (clock_ranges) {
419 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
420 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
421 return -EINVAL;
422
423 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
424 table->WatermarkRow[WM_DCFCLK][i].MinClock =
425 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
426 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
427 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
428 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
429 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
430 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
431 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
432
433 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
434 clock_ranges->reader_wm_sets[i].wm_inst;
435 }
436
437 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
438 table->WatermarkRow[WM_SOCCLK][i].MinClock =
439 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
440 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
441 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
442 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
443 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
444 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
445 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
446
447 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
448 clock_ranges->writer_wm_sets[i].wm_inst;
449 }
450
451 smu->watermarks_bitmap |= WATERMARKS_EXIST;
452 }
453
454 /* pass data to smu controller */
455 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
456 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
457 ret = smu_cmn_write_watermarks_table(smu);
458 if (ret) {
459 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
460 return ret;
461 }
462 smu->watermarks_bitmap |= WATERMARKS_LOADED;
463 }
464
465 return 0;
466 }
467
smu_v13_0_5_get_gpu_metrics(struct smu_context * smu,void ** table)468 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
469 void **table)
470 {
471 struct smu_table_context *smu_table = &smu->smu_table;
472 struct gpu_metrics_v2_1 *gpu_metrics =
473 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
474 SmuMetrics_t metrics;
475 int ret = 0;
476
477 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
478 if (ret)
479 return ret;
480
481 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
482
483 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
484 gpu_metrics->temperature_soc = metrics.SocTemperature;
485
486 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
487 gpu_metrics->average_mm_activity = metrics.UvdActivity;
488
489 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
490 gpu_metrics->average_gfx_power = metrics.Power[0];
491 gpu_metrics->average_soc_power = metrics.Power[1];
492 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
493 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
494 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
495 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
496 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
497 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
498 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
499 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
500
501 *table = (void *)gpu_metrics;
502
503 return sizeof(struct gpu_metrics_v2_1);
504 }
505
smu_v13_0_5_set_default_dpm_tables(struct smu_context * smu)506 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
507 {
508 struct smu_table_context *smu_table = &smu->smu_table;
509
510 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
511 }
512
smu_v13_0_5_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)513 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
514 long input[], uint32_t size)
515 {
516 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
517 int ret = 0;
518
519 /* Only allowed in manual mode */
520 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
521 return -EINVAL;
522
523 switch (type) {
524 case PP_OD_EDIT_SCLK_VDDC_TABLE:
525 if (size != 2) {
526 dev_err(smu->adev->dev, "Input parameter number not correct\n");
527 return -EINVAL;
528 }
529
530 if (input[0] == 0) {
531 if (input[1] < smu->gfx_default_hard_min_freq) {
532 dev_warn(smu->adev->dev,
533 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
534 input[1], smu->gfx_default_hard_min_freq);
535 return -EINVAL;
536 }
537 smu->gfx_actual_hard_min_freq = input[1];
538 } else if (input[0] == 1) {
539 if (input[1] > smu->gfx_default_soft_max_freq) {
540 dev_warn(smu->adev->dev,
541 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
542 input[1], smu->gfx_default_soft_max_freq);
543 return -EINVAL;
544 }
545 smu->gfx_actual_soft_max_freq = input[1];
546 } else {
547 return -EINVAL;
548 }
549 break;
550 case PP_OD_RESTORE_DEFAULT_TABLE:
551 if (size != 0) {
552 dev_err(smu->adev->dev, "Input parameter number not correct\n");
553 return -EINVAL;
554 } else {
555 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
556 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
557 }
558 break;
559 case PP_OD_COMMIT_DPM_TABLE:
560 if (size != 0) {
561 dev_err(smu->adev->dev, "Input parameter number not correct\n");
562 return -EINVAL;
563 } else {
564 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
565 dev_err(smu->adev->dev,
566 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
567 smu->gfx_actual_hard_min_freq,
568 smu->gfx_actual_soft_max_freq);
569 return -EINVAL;
570 }
571
572 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
573 smu->gfx_actual_hard_min_freq, NULL);
574 if (ret) {
575 dev_err(smu->adev->dev, "Set hard min sclk failed!");
576 return ret;
577 }
578
579 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
580 smu->gfx_actual_soft_max_freq, NULL);
581 if (ret) {
582 dev_err(smu->adev->dev, "Set soft max sclk failed!");
583 return ret;
584 }
585 }
586 break;
587 default:
588 return -ENOSYS;
589 }
590
591 return ret;
592 }
593
smu_v13_0_5_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)594 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
595 enum smu_clk_type clk_type,
596 uint32_t *value)
597 {
598 MetricsMember_t member_type;
599
600 switch (clk_type) {
601 case SMU_SOCCLK:
602 member_type = METRICS_AVERAGE_SOCCLK;
603 break;
604 case SMU_VCLK:
605 member_type = METRICS_AVERAGE_VCLK;
606 break;
607 case SMU_DCLK:
608 member_type = METRICS_AVERAGE_DCLK;
609 break;
610 case SMU_MCLK:
611 member_type = METRICS_AVERAGE_UCLK;
612 break;
613 case SMU_GFXCLK:
614 case SMU_SCLK:
615 return smu_cmn_send_smc_msg_with_param(smu,
616 SMU_MSG_GetGfxclkFrequency, 0, value);
617 break;
618 default:
619 return -EINVAL;
620 }
621
622 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
623 }
624
smu_v13_0_5_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)625 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
626 enum smu_clk_type clk_type,
627 uint32_t *count)
628 {
629 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
630
631 switch (clk_type) {
632 case SMU_SOCCLK:
633 *count = clk_table->NumSocClkLevelsEnabled;
634 break;
635 case SMU_VCLK:
636 *count = clk_table->VcnClkLevelsEnabled;
637 break;
638 case SMU_DCLK:
639 *count = clk_table->VcnClkLevelsEnabled;
640 break;
641 case SMU_MCLK:
642 *count = clk_table->NumDfPstatesEnabled;
643 break;
644 case SMU_FCLK:
645 *count = clk_table->NumDfPstatesEnabled;
646 break;
647 default:
648 return -EINVAL;
649 }
650
651 return 0;
652 }
653
smu_v13_0_5_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)654 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
655 enum smu_clk_type clk_type,
656 uint32_t dpm_level,
657 uint32_t *freq)
658 {
659 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
660
661 if (!clk_table || clk_type >= SMU_CLK_COUNT)
662 return -EINVAL;
663
664 switch (clk_type) {
665 case SMU_SOCCLK:
666 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
667 return -EINVAL;
668 *freq = clk_table->SocClocks[dpm_level];
669 break;
670 case SMU_VCLK:
671 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
672 return -EINVAL;
673 *freq = clk_table->VClocks[dpm_level];
674 break;
675 case SMU_DCLK:
676 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
677 return -EINVAL;
678 *freq = clk_table->DClocks[dpm_level];
679 break;
680 case SMU_UCLK:
681 case SMU_MCLK:
682 if (dpm_level >= clk_table->NumDfPstatesEnabled)
683 return -EINVAL;
684 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
685 break;
686 case SMU_FCLK:
687 if (dpm_level >= clk_table->NumDfPstatesEnabled)
688 return -EINVAL;
689 *freq = clk_table->DfPstateTable[dpm_level].FClk;
690 break;
691 default:
692 return -EINVAL;
693 }
694
695 return 0;
696 }
697
smu_v13_0_5_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)698 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
699 enum smu_clk_type clk_type)
700 {
701 enum smu_feature_mask feature_id = 0;
702
703 switch (clk_type) {
704 case SMU_MCLK:
705 case SMU_UCLK:
706 case SMU_FCLK:
707 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
708 break;
709 case SMU_GFXCLK:
710 case SMU_SCLK:
711 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
712 break;
713 case SMU_SOCCLK:
714 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
715 break;
716 case SMU_VCLK:
717 case SMU_DCLK:
718 feature_id = SMU_FEATURE_VCN_DPM_BIT;
719 break;
720 default:
721 return true;
722 }
723
724 return smu_cmn_feature_is_enabled(smu, feature_id);
725 }
726
smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)727 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
728 enum smu_clk_type clk_type,
729 uint32_t *min,
730 uint32_t *max)
731 {
732 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
733 uint32_t clock_limit;
734 uint32_t max_dpm_level, min_dpm_level;
735 int ret = 0;
736
737 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
738 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
739 if (ret)
740 return ret;
741
742 /* clock in Mhz unit */
743 if (min)
744 *min = clock_limit / 100;
745 if (max)
746 *max = clock_limit / 100;
747
748 return 0;
749 }
750
751 if (max) {
752 switch (clk_type) {
753 case SMU_GFXCLK:
754 case SMU_SCLK:
755 *max = clk_table->MaxGfxClk;
756 break;
757 case SMU_MCLK:
758 case SMU_UCLK:
759 case SMU_FCLK:
760 max_dpm_level = 0;
761 break;
762 case SMU_SOCCLK:
763 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
764 break;
765 case SMU_VCLK:
766 case SMU_DCLK:
767 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
768 break;
769 default:
770 ret = -EINVAL;
771 goto failed;
772 }
773
774 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
775 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
776 if (ret)
777 goto failed;
778 }
779 }
780
781 if (min) {
782 switch (clk_type) {
783 case SMU_GFXCLK:
784 case SMU_SCLK:
785 *min = clk_table->MinGfxClk;
786 break;
787 case SMU_MCLK:
788 case SMU_UCLK:
789 case SMU_FCLK:
790 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
791 break;
792 case SMU_SOCCLK:
793 min_dpm_level = 0;
794 break;
795 case SMU_VCLK:
796 case SMU_DCLK:
797 min_dpm_level = 0;
798 break;
799 default:
800 ret = -EINVAL;
801 goto failed;
802 }
803
804 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
805 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
806 if (ret)
807 goto failed;
808 }
809 }
810
811 failed:
812 return ret;
813 }
814
smu_v13_0_5_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)815 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
816 enum smu_clk_type clk_type,
817 uint32_t min,
818 uint32_t max,
819 bool automatic)
820 {
821 enum smu_message_type msg_set_min, msg_set_max;
822 uint32_t min_clk = min;
823 uint32_t max_clk = max;
824 int ret = 0;
825
826 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
827 return -EINVAL;
828
829 switch (clk_type) {
830 case SMU_GFXCLK:
831 case SMU_SCLK:
832 msg_set_min = SMU_MSG_SetHardMinGfxClk;
833 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
834 break;
835 case SMU_VCLK:
836 case SMU_DCLK:
837 msg_set_min = SMU_MSG_SetHardMinVcn;
838 msg_set_max = SMU_MSG_SetSoftMaxVcn;
839 break;
840 default:
841 return -EINVAL;
842 }
843
844 if (clk_type == SMU_VCLK) {
845 min_clk = min << SMU_13_VCLK_SHIFT;
846 max_clk = max << SMU_13_VCLK_SHIFT;
847 }
848
849 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
850 if (ret)
851 goto out;
852
853 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
854 if (ret)
855 goto out;
856
857 out:
858 return ret;
859 }
860
smu_v13_0_5_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)861 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
862 enum smu_clk_type clk_type, char *buf)
863 {
864 int i, idx, size = 0, ret = 0;
865 uint32_t cur_value = 0, value = 0, count = 0;
866 uint32_t min = 0, max = 0;
867
868 smu_cmn_get_sysfs_buf(&buf, &size);
869
870 switch (clk_type) {
871 case SMU_OD_SCLK:
872 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
873 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
874 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
875 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
876 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
877 break;
878 case SMU_OD_RANGE:
879 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
880 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
881 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
882 break;
883 case SMU_SOCCLK:
884 case SMU_VCLK:
885 case SMU_DCLK:
886 case SMU_MCLK:
887 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
888 if (ret)
889 goto print_clk_out;
890
891 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
892 if (ret)
893 goto print_clk_out;
894
895 for (i = 0; i < count; i++) {
896 idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
897 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);
898 if (ret)
899 goto print_clk_out;
900
901 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
902 cur_value == value ? "*" : "");
903 }
904 break;
905 case SMU_GFXCLK:
906 case SMU_SCLK:
907 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
908 if (ret)
909 goto print_clk_out;
910 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
911 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
912 if (cur_value == max)
913 i = 2;
914 else if (cur_value == min)
915 i = 0;
916 else
917 i = 1;
918 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
919 i == 0 ? "*" : "");
920 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
921 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
922 i == 1 ? "*" : "");
923 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
924 i == 2 ? "*" : "");
925 break;
926 default:
927 break;
928 }
929
930 print_clk_out:
931 return size;
932 }
933
934
smu_v13_0_5_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)935 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
936 enum smu_clk_type clk_type, uint32_t mask)
937 {
938 uint32_t soft_min_level = 0, soft_max_level = 0;
939 uint32_t min_freq = 0, max_freq = 0;
940 int ret = 0;
941
942 soft_min_level = mask ? (ffs(mask) - 1) : 0;
943 soft_max_level = mask ? (fls(mask) - 1) : 0;
944
945 switch (clk_type) {
946 case SMU_VCLK:
947 case SMU_DCLK:
948 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
949 if (ret)
950 goto force_level_out;
951
952 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
953 if (ret)
954 goto force_level_out;
955
956 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
957 if (ret)
958 goto force_level_out;
959 break;
960 default:
961 ret = -EINVAL;
962 break;
963 }
964
965 force_level_out:
966 return ret;
967 }
968
smu_v13_0_5_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk)969 static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
970 enum amd_dpm_forced_level level,
971 enum smu_clk_type clk_type,
972 uint32_t *min_clk,
973 uint32_t *max_clk)
974 {
975 int ret = 0;
976 uint32_t clk_limit = 0;
977
978 switch (clk_type) {
979 case SMU_GFXCLK:
980 case SMU_SCLK:
981 clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;
982 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
983 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
984 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
985 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
986 break;
987 case SMU_VCLK:
988 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
989 break;
990 case SMU_DCLK:
991 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
992 break;
993 default:
994 ret = -EINVAL;
995 break;
996 }
997 *min_clk = *max_clk = clk_limit;
998 return ret;
999 }
1000
smu_v13_0_5_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1001 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
1002 enum amd_dpm_forced_level level)
1003 {
1004 struct amdgpu_device *adev = smu->adev;
1005 uint32_t sclk_min = 0, sclk_max = 0;
1006 uint32_t vclk_min = 0, vclk_max = 0;
1007 uint32_t dclk_min = 0, dclk_max = 0;
1008 int ret = 0;
1009
1010 switch (level) {
1011 case AMD_DPM_FORCED_LEVEL_HIGH:
1012 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1013 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1014 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1015 sclk_min = sclk_max;
1016 vclk_min = vclk_max;
1017 dclk_min = dclk_max;
1018 break;
1019 case AMD_DPM_FORCED_LEVEL_LOW:
1020 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1021 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1022 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1023 sclk_max = sclk_min;
1024 vclk_max = vclk_min;
1025 dclk_max = dclk_min;
1026 break;
1027 case AMD_DPM_FORCED_LEVEL_AUTO:
1028 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1029 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1030 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1031 break;
1032 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1033 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1034 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1035 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1036 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1037 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1038 break;
1039 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1040 dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");
1041 return -EOPNOTSUPP;
1042 case AMD_DPM_FORCED_LEVEL_MANUAL:
1043 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1044 return 0;
1045 default:
1046 dev_err(adev->dev, "Invalid performance level %d\n", level);
1047 return -EINVAL;
1048 }
1049
1050 if (sclk_min && sclk_max) {
1051 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1052 SMU_SCLK,
1053 sclk_min,
1054 sclk_max,
1055 false);
1056 if (ret)
1057 return ret;
1058
1059 smu->gfx_actual_hard_min_freq = sclk_min;
1060 smu->gfx_actual_soft_max_freq = sclk_max;
1061 }
1062
1063 if (vclk_min && vclk_max) {
1064 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1065 SMU_VCLK,
1066 vclk_min,
1067 vclk_max,
1068 false);
1069 if (ret)
1070 return ret;
1071 }
1072
1073 if (dclk_min && dclk_max) {
1074 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1075 SMU_DCLK,
1076 dclk_min,
1077 dclk_max,
1078 false);
1079 if (ret)
1080 return ret;
1081 }
1082 return ret;
1083 }
1084
smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1085 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1086 {
1087 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1088
1089 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1090 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1091 smu->gfx_actual_hard_min_freq = 0;
1092 smu->gfx_actual_soft_max_freq = 0;
1093
1094 return 0;
1095 }
1096
1097 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
1098 .check_fw_status = smu_v13_0_check_fw_status,
1099 .check_fw_version = smu_v13_0_check_fw_version,
1100 .init_smc_tables = smu_v13_0_5_init_smc_tables,
1101 .fini_smc_tables = smu_v13_0_5_fini_smc_tables,
1102 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1103 .system_features_control = smu_v13_0_5_system_features_control,
1104 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1105 .send_smc_msg = smu_cmn_send_smc_msg,
1106 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable,
1107 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable,
1108 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables,
1109 .read_sensor = smu_v13_0_5_read_sensor,
1110 .is_dpm_running = smu_v13_0_5_is_dpm_running,
1111 .set_watermarks_table = smu_v13_0_5_set_watermarks_table,
1112 .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics,
1113 .get_enabled_mask = smu_cmn_get_enabled_mask,
1114 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1115 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1116 .gfx_off_control = smu_v13_0_gfx_off_control,
1117 .mode2_reset = smu_v13_0_5_mode2_reset,
1118 .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
1119 .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
1120 .print_clk_levels = smu_v13_0_5_print_clk_levels,
1121 .force_clk_levels = smu_v13_0_5_force_clk_levels,
1122 .set_performance_level = smu_v13_0_5_set_performance_level,
1123 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters,
1124 };
1125
smu_v13_0_5_set_ppt_funcs(struct smu_context * smu)1126 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1127 {
1128 struct amdgpu_device *adev = smu->adev;
1129
1130 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1131 smu->message_map = smu_v13_0_5_message_map;
1132 smu->feature_map = smu_v13_0_5_feature_mask_map;
1133 smu->table_map = smu_v13_0_5_table_map;
1134 smu->is_apu = true;
1135 smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION;
1136 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
1137 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
1138 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
1139 }
1140